Cypress CY7C1365C Read/Write Timing

CY7C1365C

Document #: 38-05690 Rev. *E Page 15 of 18

Read/Write Timing[17, 19, 20]

Note:

20.GW is HIGH.

Timing Diagrams (continued)

CYC

tCL

CLK

tADH

tADS

ADDRESS

tCH

tAH

tAS

tCEH

tCES

Single WRITE

D(A3)

A3 A4

BURST READBack-to-Back READs

High-Z

Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

tWEH

tWES

tOEHZ

tDH

tDS

tCDV

tOELZ

A1 A5 A6

D(A5) D(A6)

Q(A1)

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

ADSP

ADSC

BWE, BW[A:D]

ADV

Data In (D)

Data Out (Q)

[+] Feedback

Contents

Main 9-Mbit (256K x 32) Flow-Through Sync SRAM CY7C1365C Features Functional Description Selection Guide Logic Block Diagram-CY7C1365C (256K x 32) CY7C1365C Document #: 38-05690 Rev. *E Page 3 of 18 Pin Configurations 100-Pin TQFP Pinout (2 Chip Enable) (AJ version) CY7C1365C Pin Configurations CY7C1365C CY7C1365C Pin Descriptions CY7C1365C Pin Descriptions CY7C1365C Functional Overview Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics CY7C1365C Timing Diagrams Read Cycle Timing Write Cycle Timing Read/Write Timing Ordering Information Package Diagram A 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) Document History Page