Cypress CY7C1371D, CY7C1373D Switching Characteristics

CY7C1371D
CY7C1373D
Document #: 38-05556 Rev. *F Page 21 of 29
Switching Characteristics Over the Operating Range[23, 24]
Parameter Description
133 MHz 100 MHz
UnitMin Max Min Max
tPOWER[19] 11ms
Clock
tCYC Clock Cycle Time 7.5 10 ns
tCH Clock HIGH 2.1 2.5 ns
tCL Clock LOW 2.1 2.5 ns
Output Times
tCDV Data Output Valid After CLK Rise 6.5 8.5 ns
tDOH Data Output Hold After CLK Rise 2.0 2.0 ns
tCLZ Clock to Low-Z[20, 21, 22] 2.0 2.0 ns
tCHZ Clock to High-Z[20, 21, 22] 4.0 5.0 ns
tOEV OE LOW to Output Valid 3.2 3.8 ns
tOELZ OE LOW to Output Low-Z[20, 21, 22] 00ns
tOEHZ OE HIGH to Output High-Z[20, 21, 22] 4.0 5.0 ns
Setup Times
tAS Address Setup Before CLK Rise 1.5 1.5 ns
tALS ADV/LD Setup Before CLK Rise 1.5 1.5 ns
tWES WE, BWX Setup Before CLK Rise 1.5 1.5 ns
tCENS CEN Setup Before CLK Rise 1.5 1.5 ns
tDS Data Input Setup Before CLK Rise 1.5 1.5 ns
tCES Chip Enable Setup Before CLK Rise 1.5 1.5 ns
Hold Times
tAH Address Hold After CLK Rise 0.5 0.5 ns
tALH ADV/LD Hold After CLK Rise 0.5 0.5 ns
tWEH WE, BWX Hold After CLK Rise 0.5 0.5 ns
tCENH CEN Hold After CLK Rise 0.5 0.5 ns
tDH Data Input Hold After CLK Rise 0.5 0.5 ns
tCEH Chip Enable Hold After CLK Rise 0.5 0.5 ns
Notes:
19.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation
can be initiated.
20.tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
21.At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High-Z prior to Low-Z under the same system conditions.
22.This parameter is sampled and not 100% tested.
23.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
24.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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