Cypress CY7C1371D, CY7C1373D Truth Table, Partial Truth Table for Read/Write

CY7C1371D
CY7C1373D
Document #: 38-05556 Rev. *F Page 10 of 29
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used CE1CE2CE3ZZ ADV/LD WE BWXOE CEN CLK DQ
Deselect Cycle None H X X L L X X X L L->H Tri-State
Deselect Cycle None X X H L L X X X L L->H Tri-State
Deselect Cycle None X L X L L X X X L L->H Tri-State
Continue Deselect Cycle None X X X L H X X X L L->H Tri-State
Read Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q)
Read Cycle (Continue Burst) Next X X X L H X X L L L->H Data Out (Q)
NOP/Dummy Read (Begin Burst) External L H L L L H X H L L->H Tri-State
Dummy Read (Continue Burst) Next X X X L H X X H L L->H Tri-State
Write Cycle (Begin Burst) External L H L L L L L X L L->H Data In (D)
Write Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D)
NOP/Write Abort (Begin Burst) None L H L L L L H X L L->H Tri-State
Write Abort (Continue Burst) Next X X X L H X H X L L->H Tri-State
Ignore Clock Edge (Stall) Current X X X L X X X X H L->H –
Sleep Mode None X X X H X X X X X X Tri-State
Partial Truth Table for Read/Write[2, 3, 9]
Function (CY7C1371D) WE BWABWBBWCBWD
Read HXXXX
Write No bytes written L H H H H
Write Byte A – (DQA and DQPA)LLHHH
Write Byte B – (DQB and DQPB)LHLHH
Write Byte C – (D QC and DQPC)LHHLH
Write Byte D – (D QD and DQPD)LHHHL
Write All Bytes LLLLL
Partial Truth Table for Read/Write[2, 3, 9]
Function (CY7C1373D) WE BWABWB
Read HXX
Write - No bytes written L H H
Write Byte A – (DQA and DQPA)LLH
Write Byte B – (DQB and DQPB)LHL
Write All Bytes L L L
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = 0 signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BWX, and WE. See truth table for Read/Write.
4. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE
is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is based on which byte write is active.
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