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| CY7C1470V33 | |
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| CY7C1472V33 | |
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| CY7C1474V33 | |
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Identification Register Definitions |
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Instruction Field |
| CY7C1470V33 | CY7C1472V33 | CY7C1474V33 | Description | ||
| (2M x 36) | (4M x 18) | (1M x 72) | ||||
Revision Number (31:29) |
| 000 | 000 | 000 | Describes the version number | ||
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Device Depth (28:24)[12] |
| 01011 | 01011 | 01011 | Reserved for internal use | ||
Architecture/Memory |
| 001000 | 001000 | 001000 | Defines memory type and archi- | ||
Type(23:18) |
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Bus Width/Density(17:12) |
| 100100 | 010100 | 110100 | Defines width and density | ||
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Cypress JEDEC ID Code |
| 00000110100 | 00000110100 | 00000110100 | Allows unique identification of | ||
(11:1) |
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| SRAM vendor | |
ID Register Presence |
| 1 | 1 | 1 | Indicates the presence of an ID | ||
Indicator (0) |
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Scan Register Sizes
Register Name | Bit Size (x36) | Bit Size (x18) | Bit Size (x72) |
Instruction | 3 | 3 | 3 |
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Bypass | 1 | 1 | 1 |
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ID | 32 | 32 | 32 |
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Boundary Scan Order - 165 FBGA | 71 | 52 | - |
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Boundary Scan Order - 209 FBGA | - | - | 110 |
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Identification Codes
Instruction | Code | Description |
EXTEST | 000 | Captures I/O ring contents. Places the boundary scan register between TDI and TDO. |
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IDCODE | 001 | Loads the ID register with the vendor ID code and places the register between TDI |
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| and TDO. This operation does not affect SRAM operations. |
SAMPLE Z | 010 | Captures I/O ring contents. Places the boundary scan register between TDI and TDO. |
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| Forces all SRAM output drivers to a |
RESERVED | 011 | Do Not Use: This instruction is reserved for future use. |
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SAMPLE/PRELOAD | 100 | Captures I/O ring contents. Places the boundary scan register between TDI and TDO. |
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| Does not affect SRAM operation. This instruction does not implement 1149.1 preload |
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RESERVED | 101 | Do Not Use: This instruction is reserved for future use. |
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Note:
12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: | Page 15 of 29 |
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