Linear Burst Address Table Mode = GND | Cypress CY7C1474V33 specs

CY7C1470V33

CY7C1472V33

CY7C1474V33

On the next clock rise the data presented to DQ and DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474V33, DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 & DQa,b/DQPa,b for CY7C1472V33) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete.

The data written during the Write operation is controlled by BW (BWa,b,c,d,e,f,g,h for CY7C1474V33, BWa,b,c,d for CY7C1470V33 and BWa,b for CY7C1472V33) signals. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 provides Byte Write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple Byte Write operations.

Because the CY7C1470V33, CY7C1472V33, and CY7C1474V33 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474V33, DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and DQa,b/DQPa,b for CY7C1472V33) inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ and DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474V33, DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and DQa,b/DQPa,b for CY7C1472V33) are automatically tri-stated during the data portion of a Write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1470V33, CY7C1472V33, and CY7C1474V33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write opera- tions without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for

CY7C1474V33, BWa,b,c,d for CY7C1470V33 and BWa,b for CY7C1472V33) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table (MODE = Floating or VDD)

First	Second	Third	Fourth
Address	Address	Address	Address

A1,A0	A1,A0	A1,A0	A1,A0

00	01	10	11

01	00	11	10

10	11	00	01

11	10	01	00