Cypress CY7C1470V33, CY7C1472V33, CY7C1474V33 Switching Characteristics Over the Operating Range [16, 17]

CY7C1470V33
CY7C1472V33
CY7C1474V33
Document #: 38-05289 Rev. *I Page 20 of 29
Switching Characteristics Over the Operating Range [16, 17]
Parameter Description
–250 –200 –167
UnitMin. Max. Min. Max. Min. Max.
tPower[18] VCC (typical) to the First Access Read or Write 1 1 1 ms
Clock
tCYC Clock Cycle Time 4.0 5.0 6.0 ns
FMAX Maximum Operating Frequency 250 200 167 MHz
tCH Clock HIGH 2.0 2.0 2.2 ns
tCL Clock LOW 2.0 2.0 2.2 ns
Output Times
tCO Data Output Valid After CLK Rise 3.0 3.0 3.4 ns
tOEV OE LOW to Output Valid 3.0 3.0 3.4 ns
tDOH Data Output Hold After CLK Rise 1.3 1.3 1.5 ns
tCHZ Clock to High-Z[19, 20, 21] 3.0 3.0 3.4 ns
tCLZ Clock to Low-Z[19, 20, 21] 1.3 1.3 1.5 ns
tEOHZ OE HIGH to Output High-Z[19, 20, 21] 3.0 3.0 3.4 ns
tEOLZ OE LOW to Output Low-Z[19, 20, 21] 0 0 0 ns
Set-up Times
tAS Address Set-up Before CLK Rise 1.4 1.4 1.5 ns
tDS Data Input Set-up Before CLK Rise 1.4 1.4 1.5 ns
tCENS CEN Set-up Before CLK Rise 1.4 1.4 1.5 ns
tWES WE, BWx Set-up Before CLK Rise 1.4 1.4 1.5 ns
tALS ADV/LD Set-up Before CLK Rise 1.4 1.4 1.5 ns
tCES Chip Select Set-up 1.4 1.4 1.5 ns
Hold Times
tAH Address Hold After CLK Rise 0.4 0.4 0.5 ns
tDH Data Input Hold After CLK Rise 0.4 0.4 0.5 ns
tCENH CEN Hold After CLK Rise 0.4 0.4 0.5 ns
tWEH WE, BWx Hold After CLK Rise 0.4 0.4 0.5 ns
tALH ADV/LD Hold after CLK Rise 0.4 0.4 0.5 ns
tCEH Chip Select Hold After CLK Rise 0.4 0.4 0.5 ns
Notes:
16.Timing reference is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18.This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be
initiated.
19.tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
20.At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21.This parameter is sampled and not 100% tested.
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