Cypress CY7C1470V33, CY7C1472V33 Document History, ECN No Issue Date Orig. Description of Change

CY7C1470V33

CY7C1472V33

CY7C1474V33

Document History Page

Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture

Document Number: 38-05289

REV.	ECN No.	Issue Date	Orig. of	Description of Change
			Change
**	114676	08/06/02	PKS	New Data Sheet
*A	121520	01/27/03	CJM	Updated features for package offering
				Removed 300-MHz offering
				Changed tCO, tEOV, tCHZ, tEOHZ from 2.4 ns to 2.6 ns (250 MHz),
				tDOH, tCLZ from 0.8 ns to 1.0 ns (250 MHz), tDOH, tCLZ from 1.0 ns
				to 1.3 ns (200 MHz)
				Updated ordering information
				Changed Advanced Information to Preliminary
*B	223721	See ECN	NJY	Changed timing diagrams
				Changed logic block diagrams
				Modified Functional Description
				Modified “Functional Overview” section
				Added boundary scan order for all packages
				Included thermal numbers and capacitance values for all packages
				Included IDD and ISB values
				Removed 250-MHz offering and included 225-MHz speed bin
				Changed package outline for 165FBGA package and 209-ball BGA package
				Removed 119-BGA package offering
*C	235012	See ECN	RYQ	Minor Change: The data sheets do not match on the spec system and
				external web
*D	243572	See ECN	NJY	Changed ball C11,D11,E11,F11,G11 from DQPb,DQb,DQb,DQb,DQb to
				DQPa,DQa,DQa,DQa,DQa in page 4
				Modified capacitance values in page 20
*E	299511	See ECN	SYT	Removed 225-MHz offering and included 250-MHz speed bin
				Changed tCYC from 4.4 ns to 4.0 ns for 250-MHz Speed Bin
				Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for
				100 TQFP Package on Page # 20
				Added lead-free information for 100-Pin TQFP and 165 FBGA Packages
				Added comment of ‘Lead-free BG packages availability’ below the Ordering
			VBL	Information
				Add Industrial part numbers in Ordering Info section
*F	323039	See ECN	PCI	Unshaded 250 MHz speed bin in the AC/DC Table and Selection Guide
				Address expansion pins/balls in the pinouts for all packages are modified as
				per JEDEC standard
				Added Address Expansion pins in the Pin Definitions Table
				Modified VOL, VOH Test Conditions
				Changed package name from 209-ball PBGA to 209-ball FBGA on page# 5
				Removed comment of ‘Lead-free BG packages availability below the
				Ordering Information
				Updated Ordering Information Table
				Changed from Preliminary to Final
*G	351937	See ECN	PCI	Updated Ordering Information Table

Document #: 38-05289 Rev. *I Page 28 of 29

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