CY7C1470V33
CY7C1472V33
CY7C1474V33
Document #: 38-05289 Rev. *I Page 29 of 29
*H 416221 See ECN RXU Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed Three-state to Tri-state
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 18
Changed the IX current values of MODE on page # 18 from –5 µA and 30 µA
to –30 µA and 5 µA
Changed the IX current values of ZZ on page # 18 from –30 µA and 5 µA
to –5 µA and 30 µA
Changed VDDQ < VDD to VDDQ < VDD in page #18
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the Ordering Information Table
*I 472335 See ECN VKN Corrected the typo in the pin configuration for 209-Ball FBGA pinout
(Corrected the ball name for H9 to VSS from VSSQ).
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05289
REV. ECN No. Issue Date Orig. of
Change Description of Change
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