TAP Controller State Diagram

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

TEST-LOGIC

RESET

RUN-TEST/

IDLE

1	SELECT		1	SELECT
	DR-SCA N			IR-SCA N
		0			0
	1			1
	CA PTURE-DR			CA PTURE-IR
		0			0
	SHIFT-DR		0	SHIFT-IR
		1			1
	EXIT1-DR		1	EXIT1-IR
	EXIT1-DR			EXIT1-IR
		0			0
	PA USE-DR		0	PA USE-IR
		1			1
	0			0
	EXIT2-DR			EXIT2-IR
		1			1
	UPDA TE-DR			UPDA TE-IR
	1	0		1	0

Document #: 001-15029 Rev. *B

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Cypress CY7C1475BV33, CY7C1471BV33, CY7C1473BV33 manual TAP Controller State Diagram, TEST-LOGIC Reset RUN-TEST Idle

Contents

Cypress Semiconductor Corporation 198 Champion Court FeaturesSelection Guide Functional Description Description 133 MHz 117 MHz Unit Logic Block Diagram CY7C1473BV33 4M x Logic Block Diagram CY7C1471BV33 2M x Logic Block Diagram CY7C1475BV33 1M x CY7C1471BV33 Pin Configuration CY7C1473BV33 CY7C1473BV33 4M x Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M x NC/1G Ball Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M × Pin Definitions Single Read Accesses Burst Read AccessesFunctional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address TableLinear Burst Address Table Truth Table Address OperationUsed Truth Table for Read/Write Read/write truth table for CY7C1471BV33 follows.1, 2Function Ieee 1149.1 Serial Boundary Scan Jtag Disabling the Jtag FeatureTest Access Port TAP Performing a TAP Reset Overview TAP Instruction Set TEST-LOGIC Reset RUN-TEST Idle TAP Controller State Diagram Circuitry TAP Controller Block Diagram GND VIN Vddq TAP DC Electrical Characteristics and Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test Conditions TAP Timing TAP AC Switching Characteristics Register Name Bit Size Identification Register DefinitionsScan Register Sizes Identification Codes Boundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID Boundary Scan Exit Order 1M x Range Ambient Electrical CharacteristicsMaximum Ratings Operating Range 5V IO Test Load CapacitanceThermal Resistance Parameter Description Test Conditions Tqfp Fbga Unit Max Switching Characteristics Parameter Description 133 MHz 117 MHz Unit MinMin Max Read Rite Stall Switching WaveformsBW AD Address ZZ Mode Timing Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams Ball Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN/AESA Issue Orig. of Change Description of Change DateDocument History VKN/KKVTMP

Cypress CY7C1475BV33, CY7C1471BV33 TAP Controller State Diagram, TEST-LOGIC Reset RUN-TEST Idle

Models: CY7C1475BV33 CY7C1471BV33 CY7C1473BV33