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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
TAP Controller Block Diagram
1
16
32
32
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32 pages, 901.35 Kb
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Document #: 001-15029 Rev. *B
Page 16 of 32
TAP Controller Block Diagram
BypassRegister
0
Instruction Register
0
1
2
IdenticationR egister
0
1
2
29
30
31
.
.
.
BoundaryScan Register
0
1
2
.
.
x .
.
.
Selectio
n
Circuitry
TCK
TMS
TAP CONTROLLER
TDI TDO
Selectio
n
Circuitry
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Contents
Main
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
Features
Functional Description
Selection Guide
Logic Block Diagram CY7C1471BV33 (2M x 36)
C
B
DQP
Logic Block Diagram CY7C1473BV33 (4M x 18)
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Document #: 001-15029 Rev. *B Page 3 of 32
Logic Block Diagram CY7C1475BV33 (1M x 72)
DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Pin Configuration
CY7C1471BV33
Figure 1. 100-Pin TQFP Pinout
CY7C1473BV33, CY7C1475BV33
Document #: 001-15029 Rev. *B Page 5 of 32
CY7C1473BV33
Figure 2. 100-Pin TQFP Pinout
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471BV33 (2M x 36)
CY7C1473BV33 (4M x 18)
2345671 A B C D E F G H J K L M N P R
891011
2345671 A B C D E F G H J K L M N P R
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
CY7C1475BV33 (1M 72)
A B C D E F G H J K L M N P R T U V W
123456789 1110
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
Pin Definitions
Functional Overview
Single Read Accesses
Burst Read Accesses
Pin Definitions
Single Write Accesses
Interleaved Burst Address Table
Linear Burst Address Table
ZZ Mode Electrical Characteristics
Truth Table
Page
IEEE 1149.1 Serial Boundary Scan (JTAG)
Disabling the JTAG Feature
Test Access Port (TAP)
Performing a TAP Reset
TAP Registers
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
TAP Instruction Set
TAP Controller State Diagram
TAP Controller Block Diagram
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
50
TDO
50
TAP Ti min g
TAP AC Switching Characteristics
Identification Register Definitions
Scan Register Sizes
Identification Codes
Boundary Scan Exit Order (2M x 36)
Boundary Scan Exit Order (4M x 18)
Boundary Scan Exit Order (1M x 72)
Maximum Ratings
Operating Range
Electrical Characteristics
Capacitance
Thermal Resistance
Switching Characteristics
Switching Waveforms
Figure5 shows re ad-write timing waveform.[20, 21, 22] Figure 5. Read/Write Timing
DONT CARE UNDEFINED
OE
OMMAND
Page
Figure7 shows ZZ Mode timing waveform.[24, 25] Figure 7. ZZ Mode Timing
Ordering Information
Document #: 001-15029 Rev. *B Page 29 of 32
Package Diagrams
Figure 8. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm)
A
Figure 9. 165-Ball FBGA (15 x 17 x 1.4 mm)
Package Diagrams
51-85165 *A
Page
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