Ball Fbga 15 x 17 x 1.4 mm | Cypress CY7C1475BV33, CY7C1471BV33

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Package Diagrams (continued)

Figure 9. 165-Ball FBGA (15 x 17 x 1.4 mm)

TOP VIEW

PIN 1 CORNER

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

G

BOTTOM VIEW		PIN 1 CORNER
BOTTOM VIEW

					Ø0.05 M C
						Ø0.25 M C A B
					Ø0.45±0.05(165X)
11	10	9	8	7	6	5	4	3	2	1
										A
										B
1.00										C
1.00										D
										D
										E
										F
										G

0.25 C

H

J

K

L

M

N

P

R

0.53±0.05

C 0.36

-0.10

+0.05 0.35

SEATING PLANE

1.40 MAX.

0.15 C

17.00±0.10

A

	14.00	H
	14.00
		J
		K
	7.00	L
	7.00	M
		M
		N
		P
		R
		1.00
		5.00
		10.00
	B	15.00±0.10
	0.15(4X)
		51-85165 *A

Document #: 001-15029 Rev. *B

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Cypress CY7C1475BV33, CY7C1471BV33, CY7C1473BV33 manual Ball Fbga 15 x 17 x 1.4 mm

Contents

Description 133 MHz 117 MHz Unit FeaturesSelection Guide Functional Description Cypress Semiconductor Corporation 198 Champion Court Logic Block Diagram CY7C1471BV33 2M x Logic Block Diagram CY7C1473BV33 4M x Logic Block Diagram CY7C1475BV33 1M x Pin Configuration CY7C1471BV33 CY7C1473BV33 Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M x CY7C1473BV33 4M x Ball Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M × NC/1G Pin Definitions Single Read Accesses Burst Read AccessesFunctional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address TableLinear Burst Address Table Truth Table Address OperationUsed Truth Table for Read/Write Read/write truth table for CY7C1471BV33 follows.1, 2Function Performing a TAP Reset Disabling the Jtag FeatureTest Access Port TAP Ieee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Overview TAP Controller State Diagram TEST-LOGIC Reset RUN-TEST Idle TAP Controller Block Diagram Circuitry 5V TAP AC Test Conditions TAP DC Electrical Characteristics and Operating Conditions3V TAP AC Test Conditions GND VIN Vddq TAP AC Switching Characteristics TAP Timing Identification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit Size Boundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID Boundary Scan Exit Order 1M x Operating Range Electrical CharacteristicsMaximum Ratings Range Ambient Parameter Description Test Conditions Tqfp Fbga Unit Max CapacitanceThermal Resistance 5V IO Test Load Switching Characteristics Parameter Description 133 MHz 117 MHz Unit MinMin Max Rite Read Address Switching WaveformsBW AD Stall ZZ Mode Timing Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Ball Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN/KKVTMP Issue Orig. of Change Description of Change DateDocument History VKN/AESA