Rite, Read | Cypress CY7C1471BV33, CY7C1475BV33, CY7C1473BV33

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Switching Waveforms

Figure 5 shows read-write timing waveform.[20, 21, 22]

				Figure 5. Read/Write Timing
1		2	tCYC 3	4	5	6	7	8	9	10
CLK
tCENS	tCENH	tCH	tCL
CEN
tCES	tCEH

ADV/LD

W E

BW X

ADDRESS A1 A2

	tAS tAH
DQ		D(A1)
	tDS	tDH
OE
COM M AND	W RITE	W RITE
	W RITE	W RITE
	D(A1)	D(A2)

	A3	A4			A5	A6	A7
	tCDV
	tCLZ	tDOH		tOEV	tCHZ
D(A2)	D(A2+1)	Q(A3)	Q(A4)		Q(A4+1)	D(A5)	Q(A6)	D(A7)
			tOEHZ		tDOH
					tDOH
				tOELZ
BURST	READ	READ	BURST		W RITE	READ	W RITE	DESELECT
W RITE	Q(A3)	Q(A4)	READ		D(A5)	Q(A6)	D(A7)
D(A2+1)			Q(A4+1)

DON’T CARE

UNDEFINED

Notes

20.For this waveform ZZ is tied LOW.

21.When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.

22.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

Document #: 001-15029 Rev. *B

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Cypress CY7C1471BV33, CY7C1475BV33, CY7C1473BV33 manual Rite, Read

Contents

Selection Guide Functional Description FeaturesDescription 133 MHz 117 MHz Unit Cypress Semiconductor Corporation 198 Champion Court Logic Block Diagram CY7C1473BV33 4M x Logic Block Diagram CY7C1471BV33 2M x Logic Block Diagram CY7C1475BV33 1M x CY7C1471BV33 Pin Configuration CY7C1473BV33 CY7C1473BV33 4M x Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M x NC/1G Ball Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M × Pin Definitions Burst Read Accesses Single Read AccessesFunctional Overview Interleaved Burst Address Table ZZ Mode Electrical CharacteristicsLinear Burst Address Table Address Operation Truth TableUsed Read/write truth table for CY7C1471BV33 follows.1, 2 Truth Table for Read/WriteFunction Test Access Port TAP Disabling the Jtag FeaturePerforming a TAP Reset Ieee 1149.1 Serial Boundary Scan Jtag Overview TAP Instruction Set TEST-LOGIC Reset RUN-TEST Idle TAP Controller State Diagram Circuitry TAP Controller Block Diagram 3V TAP AC Test Conditions TAP DC Electrical Characteristics and Operating Conditions5V TAP AC Test Conditions GND VIN Vddq TAP Timing TAP AC Switching Characteristics Scan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit Size Boundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID Boundary Scan Exit Order 1M x Maximum Ratings Electrical CharacteristicsOperating Range Range Ambient Thermal Resistance CapacitanceParameter Description Test Conditions Tqfp Fbga Unit Max 5V IO Test Load Parameter Description 133 MHz 117 MHz Unit Min Switching CharacteristicsMin Max Read Rite BW AD Switching WaveformsAddress Stall ZZ Mode Timing Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams Ball Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Orig. of Change Description of Change DateVKN/KKVTMP VKN/AESA

Figure 5 shows read-write timing waveform.[20, 21, 22]

Figure 5. Read/Write Timing

ADV/LD

ADDRESS A1 A2

W RITE

READ

DON’T CARE