CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Document #: 001-15029 Rev. *B Page 24 of 32
Switching Characteristics
Over the Operating Range. Unless otherwise noted in the following table, timing reference level is 1.5V when VDDQ = 3.3V and is
1.25V when VDDQ = 2.5V. Test conditions shown in (a) of AC Test Loads and Waveforms on page 23 unless otherwise noted.
Parameter Description 133 MHz 117 MHz Unit
Min Max Min Max
tPOWER [16] 1 1 ms
Clock
tCYC Clock Cycle Time 7.5 10 ns
tCH Clock HIGH 2.5 3.0 ns
tCL Clock LOW 2.5 3.0 ns
Output Times
tCDV Data Output Valid After CLK Rise 6.5 8.5 ns
tDOH Data Output Hold After CLK Rise 2.5 2.5 ns
tCLZ Clock to Low-Z [17, 18, 19] 3.0 3.0 ns
tCHZ Clock to High-Z [17, 18, 19] 3.8 4.5 ns
tOEV OE LOW to Output Valid 3.0 3.8 ns
tOELZ OE LOW to Output Low-Z [17, 18, 19] 0 0 ns
tOEHZ OE HIGH to Output High-Z [17, 18, 19] 3.0 4.0 ns
Setup Times
tAS Address Setup Before CLK Rise 1.5 1.5 ns
tALS ADV/LD Setup Before CLK Rise 1.5 1.5 ns
tWES WE, BWX Setup Before CLK Rise 1.5 1.5 ns
tCENS CEN Setup Before CLK Rise 1.5 1.5 ns
tDS Data Input Setup Before CLK Rise 1.5 1.5 ns
tCES Chip Enable Setup Before CLK Rise 1.5 1.5 ns
Hold Times
tAH Address Hold After CLK Rise 0.5 0.5 ns
tALH ADV/LD Hold After CLK Rise 0.5 0.5 ns
tWEH WE, BWX Hold After CLK Rise 0.5 0.5 ns
tCENH CEN Hold After CLK Rise 0.5 0.5 ns
tDH Data Input Hold After CLK Rise 0.5 0.5 ns
tCEH Chip Enable Hold After CLK Rise 0.5 0.5 ns
Notes
16.This part has an internal voltage regulator; tPOWER is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation is initiated.
17.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 23. Transition is measured ±200mV
from steady-state voltage.
18.At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High-Z before Low-Z under the same system conditions.
19.This parameter is sampled and not 100% tested.
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