Functional Description
Features
Configurations
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
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Logic Block Diagram CY7C1511JV18
Logic Block Diagram CY7C1526JV18
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
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Logic Block Diagram CY7C1513JV18
Logic Block Diagram CY7C1515JV18
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Pin Configuration
165-Ball FBGA 15 x 17 x 1.4 mm Pinout
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Pin Configuration
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
165-Ball FBGA 15 x 17 x 1.4 mm Pinout
CY7C1511JV18, CY7C1526JV18
CY7C1513JV18, CY7C1515JV18
Pin Definitions
CY7C1513JV18, CY7C1515JV18
Pin Definitions continued
CY7C1511JV18, CY7C1526JV18
Write Operations
Single Clock Mode
Functional Overview
Read Operations
Echo Clocks
Concurrent Transactions
Depth Expansion
Programmable Impedance
CY7C1513JV18, CY7C1515JV18
CY7C1511JV18, CY7C1526JV18
Application Example
Truth Table
Write Cycle Descriptions
Write Cycle Descriptions
CY7C1513JV18, CY7C1515JV18
CY7C1511JV18, CY7C1526JV18
Write Cycle Descriptions
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Performing a TAP Reset
Disabling the JTAG Feature
Test Access Port-Test Clock
Test Mode Select TMS
BYPASS
IDCODE
SAMPLE Z
SAMPLE/PRELOAD
TAP Controller State Diagram
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Page 15 of
TAP Controller Block Diagram
TAP Electrical Characteristics
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
TAP AC Switching Characteristics
TAP Timing and Test Conditions
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Identification Register Definitions
Scan Register Sizes
Instruction Codes
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Boundary Scan Order
DLL Constraints
Power Up Sequence in QDR-II SRAM
Power Up Waveforms
Power Up Sequence
Maximum Ratings
Electrical Characteristics
DC Electrical Characteristics
AC Electrical Characteristics
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Capacitance
Thermal Resistance
AC Test Loads and Waveforms
Switching Characteristics
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Parameter
WRITE
Switching Waveforms
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
READ
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Ordering Information
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Package Diagram
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Figure 4. 165-ball FBGA 15 x 17 x 1.40 mm
Burst Architecture Document Number
Document History Page
ISSUE
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18