CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Features
Configurations
Functional Description
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Logic Block Diagram CY7C1511JV18
Logic Block Diagram CY7C1526JV18
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CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Logic Block Diagram CY7C1513JV18
Logic Block Diagram CY7C1515JV18
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CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Pin Configuration
165-Ball FBGA 15 x 17 x 1.4 mm Pinout
165-Ball FBGA 15 x 17 x 1.4 mm Pinout
Pin Configuration
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Pin Definitions
CY7C1511JV18, CY7C1526JV18
CY7C1513JV18, CY7C1515JV18
CY7C1511JV18, CY7C1526JV18
CY7C1513JV18, CY7C1515JV18
Pin Definitions continued
Read Operations
Single Clock Mode
Functional Overview
Write Operations
Programmable Impedance
Concurrent Transactions
Depth Expansion
Echo Clocks
Truth Table
CY7C1511JV18, CY7C1526JV18
Application Example
CY7C1513JV18, CY7C1515JV18
CY7C1511JV18, CY7C1526JV18
Write Cycle Descriptions
CY7C1513JV18, CY7C1515JV18
Write Cycle Descriptions
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Write Cycle Descriptions
Test Mode Select TMS
Disabling the JTAG Feature
Test Access Port-Test Clock
Performing a TAP Reset
SAMPLE/PRELOAD
IDCODE
SAMPLE Z
BYPASS
Page 15 of
TAP Controller State Diagram
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
TAP Controller Block Diagram
TAP Electrical Characteristics
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
TAP AC Switching Characteristics
TAP Timing and Test Conditions
Instruction Codes
Identification Register Definitions
Scan Register Sizes
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Boundary Scan Order
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Power Up Sequence
Power Up Sequence in QDR-II SRAM
Power Up Waveforms
DLL Constraints
AC Electrical Characteristics
Electrical Characteristics
DC Electrical Characteristics
Maximum Ratings
AC Test Loads and Waveforms
Capacitance
Thermal Resistance
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Parameter
Switching Characteristics
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
READ
Switching Waveforms
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
WRITE
Ordering Information
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Figure 4. 165-ball FBGA 15 x 17 x 1.40 mm
Package Diagram
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
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CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Document History Page
ISSUE
Burst Architecture Document Number