Cypress CY7C1526JV18 manual Logic Block Diagram CY7C1513JV18, Logic Block Diagram CY7C1515JV18

CY7C1511JV18, CY7C1526JV18

CY7C1513JV18, CY7C1515JV18

Logic Block Diagram (CY7C1513JV18)

18

D[17:0]

20Address

A(19:0) Register

K

K CLK

Gen.

DOFF

	Write	Write	Write	Write
	Reg	Reg	Reg	Reg
Write Add. Decode	1M x 18 Array	1M x 18 Array	1M x 18 Array	1M x 18 Array	Read Add. Decode
	Read Data Reg.

Address Register

Control

Logic

20 A(19:0)

RPS

C

C

VREF
		Control
WPS
		Logic
BWS
	[1:0]

							CQ
72	36			18		CQ
		Reg.	Reg.
				18	18
	36	Reg.		18		Q[17:0]
				18

Logic Block Diagram (CY7C1515JV18)

36

D[35:0]

19Address

A(18:0) Register

K

K CLK

Gen.

DOFF

	Write	Write	Write	Write
	Reg	Reg	Reg	Reg
Decode	512K x	512K x	512K x	512K x	Decode
Write Add.	36 Array	36 Array	36 Array	36 Array	Read Add.
	Read Data Reg.

Address Register

Control

Logic

19 A(18:0)

RPS

C

C

VREF
		Control
WPS
		Logic
BWS
	[3:0]

							CQ
144	72			36		CQ
		Reg.	Reg.
				36	36
	72	Reg.		36		Q[35:0]
				36

Document Number: 001-12560 Rev. *C Page 3 of 27

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