Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress manual Ordering Information, CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18

Models: CY7C1511JV18 CY7C1513JV18 CY7C1526JV18 CY7C1515JV18

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Ordering Information

CY7C1511JV18, CY7C1526JV18

CY7C1513JV18, CY7C1515JV18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
300	CY7C1511JV18-300BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1526JV18-300BZC

	CY7C1513JV18-300BZC

	CY7C1515JV18-300BZC

	CY7C1511JV18-300BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1526JV18-300BZXC

	CY7C1513JV18-300BZXC

	CY7C1515JV18-300BZXC

	CY7C1511JV18-300BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1526JV18-300BZI

	CY7C1513JV18-300BZI

	CY7C1515JV18-300BZI

	CY7C1511JV18-300BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1526JV18-300BZXI

	CY7C1513JV18-300BZXI

	CY7C1515JV18-300BZXI

Document Number: 001-12560 Rev. *C

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Cypress manual Ordering Information, CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18

Contents

Configurations FeaturesCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Functional DescriptionLogic Block Diagram CY7C1526JV18 Logic Block Diagram CY7C1511JV18CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 + FeedbackLogic Block Diagram CY7C1515JV18 Logic Block Diagram CY7C1513JV18CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 + Feedback165-Ball FBGA 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Pin Configuration165-Ball FBGA 15 x 17 x 1.4 mm Pinout CY7C1513JV18, CY7C1515JV18 CY7C1511JV18, CY7C1526JV18Pin Definitions Pin Definitions continued CY7C1513JV18, CY7C1515JV18CY7C1511JV18, CY7C1526JV18 Functional Overview Single Clock ModeRead Operations Write OperationsDepth Expansion Concurrent TransactionsProgrammable Impedance Echo ClocksApplication Example CY7C1511JV18, CY7C1526JV18Truth Table CY7C1513JV18, CY7C1515JV18CY7C1513JV18, CY7C1515JV18 Write Cycle DescriptionsCY7C1511JV18, CY7C1526JV18 Write Cycle DescriptionsWrite Cycle Descriptions CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18Test Access Port-Test Clock Disabling the JTAG FeatureTest Mode Select TMS Performing a TAP ResetSAMPLE Z IDCODESAMPLE/PRELOAD BYPASSCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 TAP Controller State DiagramPage 15 of TAP Electrical Characteristics TAP Controller Block DiagramCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 TAP Timing and Test Conditions TAP AC Switching CharacteristicsCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Scan Register Sizes Identification Register DefinitionsInstruction Codes CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Boundary Scan OrderPower Up Waveforms Power Up Sequence in QDR-II SRAMPower Up Sequence DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsThermal Resistance CapacitanceAC Test Loads and Waveforms CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Switching CharacteristicsParameter CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Switching WaveformsREAD WRITECY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Ordering InformationCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Package DiagramFigure 4. 165-ball FBGA 15 x 17 x 1.40 mm + FeedbackISSUE Document History PageCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Burst Architecture Document Number