Cypress CY7C1513JV18 manual CY7C1511JV18, CY7C1526JV18, Application Example, Truth Table, Asic

						CY7C1511JV18, CY7C1526JV18
						CY7C1513JV18, CY7C1515JV18
Application Example
Figure 1 shows four QDR-II used in an application.
			Figure 1. Application Example
			SRAM #1		ZQ	R = 250ohms	SRAM #4		ZQ	R = 250ohms
	Vt		R W B		CQ/CQ#		R W B		CQ/CQ#
		D	P P W		Q	D	P P W		Q
	R		S S S				S S S
		A		C C# K K#
			# # #			A	# # #	C C# K K#
	DATA IN
	DATA OUT						Vt
	Address						Vt
BUS	RPS#						R
	WPS#
MASTER
	BWS#
(CPU
	CLKIN/CLKIN#
or	Source K
ASIC)
	Source K#
	Delayed K
	Delayed K#
	R	R = 50ohms	Vt = Vddq/2
Truth Table
The truth table for CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, and CY7C1515JV18 follows. [2, 3, 4, 5, 6, 7]

Operation	K	RPS	WPS	DQ		DQ		DQ	DQ
Write Cycle:	L-H	H [8]	L [9]	D(A) at K(t + 1)↑		D(A + 1) at		D(A + 2) at K(t + 2)↑
							K(t + 1)↑		D(A + 3) at K(t + 2)↑
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
Read Cycle:	L-H	L [9]	X	Q(A) at		Q(A + 1) at C(t + 2)↑			Q(A + 3) at C(t + 3)↑
					C(t + 1)↑			Q(A + 2) at C(t + 2)↑
Load address on the rising
edge of K; wait one and a
half cycle; read data on
two consecutive C and C
rising edges.
NOP: No Operation	L-H	H	H	D = X		D = X		D = X	D = X
				Q = High-Z		Q = High-Z		Q = High-Z	Q = High-Z
Standby: Clock Stopped	Stopped	X	X	Previous State		Previous State		Previous State	Previous State

Notes

2.X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.

3.Device powers up deselected with the outputs in a tri-state condition.

4.“A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.

5.“t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.

6.Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7.It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

8.If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.

9.This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the second read or write request.

Document Number: 001-12560 Rev. *C Page 10 of 27

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