Cypress CY7C1513JV18 Power Up Sequence in QDR-II SRAM, Power Up Waveforms, DLL Constraints, ~ ~

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18

Power Up Sequence in QDR-II SRAM

QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.

Power Up Sequence

■Apply power and drive DOFF HIGH (All other inputs can be HIGH or LOW).

❐Apply VDD before VDDQ.

❐Apply VDDQ before VREF or at the same time as VREF.

■Provide stable power and clock (K, K) for 1024 cycles to lock the DLL.

Power Up Waveforms

DLL Constraints

■DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var.

■The DLL functions at frequencies down to 120 MHz.

■If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 1024 cycles stable clock to relock to the desired clock frequency.

~ ~

K

K

	~ ~
Unstable Clock	> 1024 Stable clock	Start Normal
		Operation

Clock Start (Clock Starts after VDD/ V DDQ Stable)

VDD/ VDDQ VDD/ V DDQ Stable (< +/- 0.1V DC per 50ns )

Fix High (or tied to VDDQ)

DOFF

Document Number: 001-12560 Rev. *C Page 20 of 27

[+] Feedback