CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Switching Waveforms
Read/Write/Deselect Sequence [29, 30, 31, 32]
Figure 5. Waveform for 2.0 Cycle Read Latency
NOP
1
K
tKH
| READ | READ | NOP | NOP | NOP | WRITE | WRITE | READ | NOP | NOP |
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| 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 |
tKL | tCYC | tKHKH |
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K
LD 
tSC tHC
R/W
A | A0 | A1 |
| A2 | A3 | A4 |
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| tSA tHA | tQVLD |
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| tQVLD |
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QVLD |
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| tHD | tHD |
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| tSD |
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DQ |
| Q00 | Q01 Q10 | Q11 | D21 | D30 D31 | Q40 Q41 |
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| tCLZ | tDOH | tCHZ |
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| tCO |
| tCQD |
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| (Read Latency = 2.0 Cycles) |
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| tCCQO | tCQDOH |
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| tCQOH |
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CQ |
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| t CCQO |
| tCQH | tCQHCQH |
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| tCQOH |
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CQ |
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| DON’T CARE | UNDEFINED |
Notes
29.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
30.Outputs are disabled
31.The third NOP cycle between read to write transition is not necessary for correct device operation when Read Latency = 2.0 cycles; however at high frequency operation, it is required to avoid bus contention.
32.In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: | Page 24 of 28 |
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