Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress CY7C1550V18, CY7C1548V18, CY7C1546V18, CY7C1557V18 manual Ordering Information continued

Models: CY7C1557V18 CY7C1546V18 CY7C1550V18 CY7C1548V18

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Ordering Information (continued)

CY7C1546V18, CY7C1557V18

CY7C1548V18, CY7C1550V18

Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
300	CY7C1546V18-300BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1557V18-300BZC

	CY7C1548V18-300BZC

	CY7C1550V18-300BZC

	CY7C1546V18-300BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1557V18-300BZXC

	CY7C1548V18-300BZXC

	CY7C1550V18-300BZXC

	CY7C1546V18-300BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1557V18-300BZI

	CY7C1548V18-300BZI

	CY7C1550V18-300BZI

	CY7C1546V18-300BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1557V18-300BZXI

	CY7C1548V18-300BZXI

	CY7C1550V18-300BZXI

Document Number: 001-06550 Rev. *E

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Cypress manual Ordering Information continued, CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18

Contents

CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 FeaturesConfigurations Functional DescriptionCY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Logic Block Diagram CY7C1546V18Logic Block Diagram CY7C1557V18 + FeedbackCY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Logic Block Diagram CY7C1548V18Logic Block Diagram CY7C1550V18 + FeedbackCY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Pin Configuration165-Ball FBGA 15 x 17 x 1.4 mm Pinout 165-Ball FBGA 15 x 17 x 1.4 mm Pinout Pin Configuration continuedCY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Pin Definitions CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 CY7C1548V18, CY7C1550V18 Pin Definitions continuedCY7C1546V18, CY7C1557V18 Read Operations CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18Functional Overview Write OperationsEcho Clocks Valid Data Indicator QVLDApplication Example CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Write Cycle DescriptionsTruth Table Write Cycle Descriptions CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18Write Cycle Descriptions Test Mode Select TMS Disabling the JTAG FeatureTest Access Port-Test Clock Performing a TAP ResetSAMPLE/PRELOAD IDCODESAMPLE Z BYPASSPage 14 of TAP Controller State DiagramCY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 TAP Controller Block DiagramTAP Electrical Characteristics CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 TAP AC Switching CharacteristicsTAP Timing and Test Conditions Instruction Codes Identification Register DefinitionsScan Register Sizes CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18Boundary Scan Order CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18Power Up Sequence Power Up Sequence in DDR-II+ SRAMPower Up Waveforms DLL ConstraintsMaximum Ratings Electrical CharacteristicsDC Electrical Characteristics Operating RangeThermal Resistance AC Electrical CharacteristicsCapacitance Electrical CharacteristicsFigure 4. AC Test Loads and Waveforms AC Test Loads and WaveformsCY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 + FeedbackParameter Switching CharacteristicsCY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Switching WaveformsRead/Write/Deselect Sequence 29, 30, 31 Ordering Information CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18Ordering Information continued CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18Figure 6. 165-Ball FBGA 15 x 17 x 1.4 mm Package DiagramCY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 + FeedbackCY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Document History PageIssue Document Number