Cypress CY7C1557V18 manual TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag

				CY7C1546V18, CY7C1557V18
				CY7C1548V18, CY7C1550V18
Pin Definitions (continued)
	Pin Name	IO		Pin Description
	ZQ	Input	Output Impedance Matching Input. This input is used to tune the device outputs to the system data
			bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
			connected between ZQ and ground. Alternatively, this pin is connected directly to VDDQ and enables
			the minimum impedance mode. This pin is not connected directly to GND or left unconnected.
		Input	DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
	DOFF
			timing in the DLL turned off operation is different from that listed in this datasheet. For normal
			operation, this pin is connected to a pull up through a 10 Kohm or less pull up resistor. The device
			behaves in DDR-I mode when the DLL is turned off. In this mode, the device is operated at a
			frequency of up to 167 MHz with DDR-I timing.
	TDO	Output	TDO for JTAG.
	TCK	Input	TCK Pin for JTAG.
	TDI	Input	TDI Pin for JTAG.
	TMS	Input	TMS Pin for JTAG.
	NC	N/A	Not Connected to the Die. Is tied to any voltage level.
	NC/72M	N/A	Not Connected to the Die. Is tied to any voltage level.
	NC/144M	N/A	Not Connected to the Die. Is tied to any voltage level.
	NC/288M	N/A	Not Connected to the Die. Is tied to any voltage level.
	VREF	Input	Reference Voltage Input. Static input is used to set the reference level for HSTL inputs, outputs,
		Reference	and AC measurement points.
	VDD	Power Supply	Power Supply Inputs to the Core of the Device.
	VSS	Ground	Ground for the Device.
	VDDQ	Power Supply	Power Supply Inputs for the Outputs of the Device.

Document Number: 001-06550 Rev. *E Page 7 of 28

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