Cypress Document History Page, CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18, ECN No, Date

Models: CY7C1557V18 CY7C1546V18 CY7C1550V18 CY7C1548V18

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Document History Page

CY7C1546V18, CY7C1557V18

CY7C1548V18, CY7C1550V18

Document History Page

Document Title: CY7C1546V18/CY7C1557V18/CY7C1548V18/CY7C1550V18, 72-Mbit DDR-II+ SRAM 2-Word Burst Architec- ture (2.0 Cycle Read Latency)

Document Number: 001-06550

REV.

ECN No.

Issue

Orig. of

Description of Change

Date

Change

 

 

 

 

 

 

 

 

**

432718

See ECN

NXR

New datasheet

 

 

 

 

 

*A

437000

See ECN

IGS

ECN for show on web

 

 

 

 

 

*B

461934

See ECN

NXR

Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH

 

 

 

 

from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching

 

 

 

 

Characteristics table

 

 

 

 

Modified Power up waveform

*C

497567

See ECN

NXR

Changed the VDDQ operating voltage to 1.4V to VDD in the Features section, Operating

 

 

 

 

Range table, and the DC Electrical Characteristics table

 

 

 

 

Added foot note in page 1

 

 

 

 

Changed the Maximum rating of ambient temperature with power applied from –10°C

 

 

 

 

to +85°C to –55°C to +125°C

 

 

 

 

Changed VREF (Max) specification from 0.85V to 0.95V in the DC Electrical Character-

 

 

 

 

istics table and in the note below the table

 

 

 

 

Updated footnote 18 to specify overshoot and undershoot specifications

 

 

 

 

Updated IDD and ISB values

 

 

 

 

Updated ΘJA and ΘJC values

 

 

 

 

Removed x9 part and its related information

 

 

 

 

Updated footnote 25

*D

1351504

See ECN

VKN/AESA

Converted from preliminary to final

 

 

 

 

Added x8 and x9 parts

 

 

 

 

Updated logic block diagram for x18 and x36 parts

 

 

 

 

Changed tCYC max spec to 8.4 ns for all speed bins

 

 

 

 

Updated footnote# 21

 

 

 

 

Updated Ordering Information table

*E

2193266

See ECN

VKN/AESA

Added footnote# 20 related to IDD

© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-06550 Rev. *E

Revised March 11, 2008

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QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

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Cypress Document History Page, CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18, Document Number, ECN No, Issue, Date