Cypress CY7C1557V18, CY7C1546V18 Logic Block Diagram CY7C1548V18, Logic Block Diagram CY7C1550V18

CY7C1546V18, CY7C1557V18

CY7C1548V18, CY7C1550V18

Logic Block Diagram (CY7C1548V18)

A(20:0)			21
							Address
							Register
				LD
					K	CLK
					K
							Gen.
	DOFF
	VREF
							Control
		R/W
							Logic
		BWS
						[1:0]

Write	Write
Reg	Reg

Write Add. Decode	2M x 18 Array	2M x 18 Array
	Read Data Reg.
		36
		18
		18

Read Add. Decode

							18
	Output
		Logic
					R/W
	Control
				18					CQ
Reg.			Reg.					CQ
								DQ[17:0]
Reg.				18	18
								QVLD

Logic Block Diagram (CY7C1550V18)

A(19:0)			20
							Address
							Register
				LD
					K	CLK
					K
							Gen.
	DOFF
	VREF
							Control
		R/W
							Logic
		BWS
						[3:0]

Write

Write

Reg

Reg

DecodeAdd.Write

1Mx36Array

1Mx36Array

DecodeAdd.Read

Logic

R/W

36

Output

Control

Read Data Reg.

72

36

36

CQ

Reg.

Reg.

CQ

36

DQ[35:0]

Reg.

36

36

QVLD

Document Number: 001-06550 Rev. *E Page 3 of 28

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