Functional Description
Features
Configurations
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
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Logic Block Diagram CY7C1546V18
Logic Block Diagram CY7C1557V18
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
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Logic Block Diagram CY7C1548V18
Logic Block Diagram CY7C1550V18
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Pin Configuration
165-Ball FBGA 15 x 17 x 1.4 mm Pinout
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Pin Configuration continued
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
165-Ball FBGA 15 x 17 x 1.4 mm Pinout
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Pin Definitions
Pin Definitions continued
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Write Operations
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Functional Overview
Read Operations
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Valid Data Indicator QVLD
Application Example
Echo Clocks
Write Cycle Descriptions
Truth Table
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Write Cycle Descriptions
Write Cycle Descriptions
IEEE 1149.1 Serial Boundary Scan JTAG
Disabling the JTAG Feature
Test Access Port-Test Clock
Performing a TAP Reset
BYPASS
IDCODE
SAMPLE Z
SAMPLE/PRELOAD
TAP Controller State Diagram
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Page 14 of
TAP Controller Block Diagram
TAP Electrical Characteristics
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
TAP AC Switching Characteristics
TAP Timing and Test Conditions
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Identification Register Definitions
Scan Register Sizes
Instruction Codes
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Boundary Scan Order
DLL Constraints
Power Up Sequence in DDR-II+ SRAM
Power Up Waveforms
Power Up Sequence
Operating Range
Electrical Characteristics
DC Electrical Characteristics
Maximum Ratings
Electrical Characteristics
AC Electrical Characteristics
Capacitance
Thermal Resistance
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AC Test Loads and Waveforms
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Figure 4. AC Test Loads and Waveforms
Switching Characteristics
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Parameter
Switching Waveforms
Read/Write/Deselect Sequence 29, 30, 31
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Ordering Information
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Ordering Information continued
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Package Diagram
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Figure 6. 165-Ball FBGA 15 x 17 x 1.4 mm
Document Number
Document History Page
Issue
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18