Configurations
Features
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Functional Description
Logic Block Diagram CY7C1557V18
Logic Block Diagram CY7C1546V18
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
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Logic Block Diagram CY7C1550V18
Logic Block Diagram CY7C1548V18
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
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165-Ball FBGA 15 x 17 x 1.4 mm Pinout
Pin Configuration
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Pin Configuration continued
165-Ball FBGA 15 x 17 x 1.4 mm Pinout
CY7C1548V18, CY7C1550V18
CY7C1546V18, CY7C1557V18
Pin Definitions
CY7C1546V18, CY7C1557V18
Pin Definitions continued
CY7C1548V18, CY7C1550V18
Functional Overview
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Read Operations
Write Operations
Application Example
Valid Data Indicator QVLD
Echo Clocks
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Truth Table
Write Cycle Descriptions
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Write Cycle Descriptions
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Write Cycle Descriptions
Test Access Port-Test Clock
Disabling the JTAG Feature
Performing a TAP Reset
IEEE 1149.1 Serial Boundary Scan JTAG
SAMPLE Z
IDCODE
SAMPLE/PRELOAD
BYPASS
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
TAP Controller State Diagram
Page 14 of
TAP Electrical Characteristics
TAP Controller Block Diagram
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
TAP Timing and Test Conditions
TAP AC Switching Characteristics
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Scan Register Sizes
Identification Register Definitions
Instruction Codes
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Boundary Scan Order
Power Up Waveforms
Power Up Sequence in DDR-II+ SRAM
Power Up Sequence
DLL Constraints
DC Electrical Characteristics
Electrical Characteristics
Maximum Ratings
Operating Range
Capacitance
AC Electrical Characteristics
Thermal Resistance
Electrical Characteristics
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Switching Characteristics
Parameter
Read/Write/Deselect Sequence 29, 30, 31
Switching Waveforms
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Ordering Information
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Ordering Information continued
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Package Diagram
Figure 6. 165-Ball FBGA 15 x 17 x 1.4 mm
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Issue
Document History Page
CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18
Document Number