Cypress CY7C1546V18, CY7C1548V18 manual Application Example, Echo Clocks, Valid Data Indicator QVLD

CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18

Echo Clocks

Echo clocks are provided on the DDR-II+ to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II+. CQ is referenced with respect to K and CQ is refer- enced with respect to K. These are free-running clocks and are synchronized to the input clock of the DDR-II+. The timing for the echo clocks is shown in Switching Characteristics on page 23.

Valid Data Indicator (QVLD)

QVLD is provided on the DDR-II+ to simplify data capture on high speed systems. The QVLD is generated by the DDR-II+ device along with data output. This signal is also edge aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives.

DLL

These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in DDR-I mode (with 1.0 cycle latency and a longer access time). For more information, refer to the application note, “DLL Consid- erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30ns. However, it is not necessary to reset the DLL to lock to the desired frequency. During Power-up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock.

Application Example

Figure 1 shows two DDR-II+ used in an application.

Figure 1. Application Example

SRAM#1

ZQ

SRAM#2

ZQ

DQ

CQ/CQ

R = 250ohms

DQ

CQ/CQ

R = 250ohms

A

LD

R/W

K

K

A

LD

R/W

K

K

DQ

BUS

Addresses

MASTER

Cycle Start

(CPU or ASIC)

R/W

Source CLK

Source CLK

Echo Clock1/Echo Clock1

Echo Clock2/Echo Clock2

Document Number: 001-06550 Rev. *E Page 9 of 28

[+] Feedback