STK14CA8
Document Number: 001-51592 Rev. ** Page 12 of 16
Software STORE
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The STK14CA8
software STORE cycle is initiated by executing sequential E
controlled or G controlled READ cycles from six specific address
locations in exact order. During the STORE cycle, previous data
is erased and then the new data is programmed into the nonvol-
atile elements. After a STORE cycle is initiated, further memory
inputs and outputs are disabled until the cycle is completed.
To initiate the software STORE cycle, the following READ
sequence must be performed:
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence
and that G is active. After the t
STORE
cycle time is fulfilled, the
SRAM is again activated for READ and WRITE operation.
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of E controlled or G
controlled READ operations must be performed:
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is trans-
ferred into the SRAM cells. After the t
RECALL
cycle time, the
SRAM is again ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the nonvolatile
storage elements.
Data Protection
The STK14CA8 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and
WRITE operations. The low voltage condition is detected when
V
CC
<V
SWITCH
.
If the STK14CA8 is in a WRITE mode (both E and W low) at
power up, after a RECALL, or after a STORE, the WRITE is
inhibited until a negative transition on E or W is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Noise Considerations
The STK14CA8 is a high speed memory and so must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
CC
and V
SS
, using leads and traces that are a short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
End product’s firmware should not assume an NV array is in a
set programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, etc. should always program a unique NV
pattern (for example, complex 4-byte pattern of 46 E6 49 53
hex or more random bytes) as part of the final system manufac-
turing test to ensure these system routines work consistently.
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state such as AutoStore enabled. While the
nvSRAM is shipped in a preset state, best practice is to again
rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently (program
bugs, incoming inspection routines, and so on.)
■
If AutoStore is firmware disabled, it does not reset to “AutoStore
enabled” on every power down event captured by the nvSRAM.
The application firmware should re-enable or re-disable
AutoStore on each reset sequence based on the behavior
desired.
■
The V
cap
value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the max V
cap
value because the
nvSRAM internal algorithm calculates V
cap
charge time based
on this max Vcap value. Customers that want to use a larger
V
cap
value to make sure there is extra store charge and store
time should discuss their V
cap
size selection with Cypress to
understand any impact on the V
cap
voltage level at the end of
a t
RECALL
period.
Read Address 0x4E38 Valid READ
Read Address 0xB1C7 Valid READ
Read Address 0x83E0 Valid READ
Read Address 0x7C1F Valid READ
Read Address 0x703F Valid READ
Read Address 0x8FC0 Initiate STORE Cycle
Read Address 0x4E38 Valid READ
Read Address 0xB1C7 Valid READ
Read Address 0x83E0 Valid READ
Read Address 0x7C1F Valid READ
Read Address 0x703F Valid READ
Read Address 0x4C63 Initiate RECALL Cycle
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