STK17TA8
Document #: 001-52039 Rev. ** Page 6 of 23
SRAM READ Cycles #1 and #2
Figure 5. SRAM READ Cycle #1: Address Controlled[3, 4, 6]
Figure 6. SRAM READ Cycle #2: E and G Controlled[3, 6]
Notes
3. W must be high during SRAM READ cycles.
4. Device is continuously selected with E and G both low
5. Measured ± 200mV from steady state output voltage.
6. HSB must remain high during READ and WRITE cycles.
NO. Symbols Parameter STK17TA8-25 STK17TA8-45 Units
#1 #2 Alt. Min Max Min Max
1t
ELQV tACS Chip Enable Access Time 25 45 ns
2t
AVAV[3] tELEH[3] tRC Read Cycle Time 25 45 ns
3t
AVQV[4] tAVQ V[4] tAA Address Access Time 25 45 ns
4t
GLQV tOE Output Enable to Data Valid 12 20 ns
5t
AXQX[4] tAXQX[4] tOH Output Hold after Address Change 3 3 ns
6t
ELQX tLZ Address Change or Chip Enable to Output Active 3 3 ns
7t
EHQZ[5] tHZ Address Change or Chip Disable to Output
Inactive
10 15 ns
8t
GLQX tOLZ Output Enable to Output Active 0 0 ns
9t
GHQZ[5] tOHZ Output Disable to Output Inactive 10 15 ns
10 tELICCL[2] tPA Chip Enable to Power Active 0 0 ns
11 tEHICCH[2] tPS Chip Disable to Power Standby 25 45 ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
229
11
7
9
10
8
4
3
6
1
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