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SRAM WRITE Cycles #1 and #2 |
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| NO. |
| Symbols |
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| Parameter | Units |
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| #1 |
| #2 |
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| Alt. | Min | Max | Min | Max |
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11 | tAVAV |
| tAVAV |
| tWC | Write Cycle Time | 25 |
| 45 |
| ns |
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13 | tWLWH |
| tWLEH |
| tWP | Write Pulse Width | 20 |
| 30 |
| ns |
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14 | tELWH |
| tELEH |
| tCW | Chip Enable to End of Write | 20 |
| 30 |
| ns |
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15 | tDVWH |
| tDVEH |
| tDW | Data | 10 |
| 15 |
| ns |
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16 | tWHDX |
| tEHDX |
| tDH | Data Hold after End of Write | 0 |
| 0 |
| ns |
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17 | tAVWH |
| tAVEH |
| tAW | Address | 20 |
| 30 |
| ns |
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18 | tAVWL |
| tAVEL |
| tAS | Address | 0 |
| 0 |
| ns |
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19 | tWHAX |
| tEHAX |
| tWR | Address Hold after End of Write | 0 |
| 0 |
| ns |
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20 | tWLQZ5, 7 |
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| tWZ | Write Enable to Output Disable |
| 10 |
| 15 | ns |
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21 | tWHQX |
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| tOW | Output Active after End of Write | 3 |
| 3 |
| ns |
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Figure 7. SRAM WRITE Cycle #1: W Controlled[7, 8]
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ADDRESS |
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| 14 | 19 |
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| tWHAX | |
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| tELWH |
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E |
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| 17 |
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| 18 |
| tAVWH |
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| tAVWL |
| 13 |
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W |
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| tWLWH |
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| 15 | 16 |
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| tDVWH | tWHDX |
DATA IN |
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| 20 |
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| tWLQZ | 21 |
DATA OUT |
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| HIGH IMPEDANCE | tWHQX |
| PREVIOUS DATA |
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Figure 8. SRAM WRITE Cycle #2: E Controlled[7, 8]
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ADDRESS |
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18 |
| 14 | 19 |
tAVEL |
| tELEH | tEHAX |
E |
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| 17 |
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| tAVEH | 13 |
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W |
| tWLEH |
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| 15 | 16 |
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| tDVEH | tEHDX |
DATA IN |
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| DATA VALID |
DATA OUT |
| HIGH IMPEDANCE |
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Notes
7.If W is low when E goes low, the outputs remain in the
8.E or W must be ≥ VIH during address transitions.
Document #: | Page 7 of 23 |
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