Cypress STK17TA8

STK17TA8

Document #: 001-52039 Rev. ** Page 22 of 23

Package Diagrams

Figure 17. 48-Pin SSOP (51-85061)

51-85061 *C

[+] Feedback

Contents

Main STK17TA8 128k X 8 AutoStore nvSRAM with Real Time Clock Features Description Logic Block Diagram Document #: 001-52039 Rev. ** Page 2 of 23 Pinouts [+] Feedback (TOP) Pin Descriptions Note 1. For detailed package size specifications, See Package Diagrams on page22.. Absolute Maximum Ratings RF (SSOP-48) Package Thermal Characteristics DC Electrical Characteristics AC Test Conditions Capacitance DC Electrical Characteristics RTC DC Characteristics I V V t SRAM READ Cycles #1 and #2 STK17TA8 Document #: 001-52039 Rev. ** Page 7 of 23 [+] Feedback SRAM WRITE Cycles #1 and #2 Figure 7. SRAM WRITE Cycle #1: W Controlled[7, 8] STK17TA8 AutoStore/Power Up Recall Software-Controlled STORE/RECALL Cycle Hardware STORE Cycle Soft Sequence Commands MODE Selection nvSRAM Operation SRAM READ SRAM WRITE AutoStore Operation Hardware STORE (HSB) Operation Software RECALL Data Protection Noise Considerations Preventing AutoStore Best Practices RTC Operations Real Time Clock Reading The Clock Setting The Clock Backup Power Calibrating The Clock Alarm Watchdog Timer Power Monitor Interrupts Interrupt Register Flags Register STK17TA8 RTC Register Page Page Register Map Detail Ordering Information Ordering Codes STK17TA8-R F 45 ITR Page Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions