Cypress STK17TA8 manual 0x1FFF2 Alarm Seconds, 0x1FFF1 Real Time Clock Centuries 10s Centuries

									STK17TA8
Register Map Detail (continued)
0x1FFF2					Alarm – Seconds
	D7	D6		D5	D4	D3	D2	D1	D0
	M		10s	Alarm Seconds			Alarm Seconds

Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.

MMatch. Setting this bit to 0 causes the seconds’ value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the seconds value.

0x1FFF1			Real Time Clock – Centuries
D7	D6	D5	D4	D3	D2	D1	D0
	10s Centuries			Centuries

Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries.

0x1FFF0					Flags
	D7	D6	D5	D4		D3	D2	D1	D0
	WDF	AF	PF	OSCF		0	CAL	W	R
WDF	Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without being
	reset by the user. It is cleared to 0 when the Flags register is read or on power-up.
AF	Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the alarm registers
	with the match bits = 0. It is cleared when the Flags register is read or on power-up.
PF	Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail threshold VSWITCH. It is cleared
	to 0 when the Flags register is read or on power-up.
OSCF	Oscillator Fail Flag. Set to 1 on power-up only if the oscillator is enabled and not running in the first 5ms of operation.
	This indicates that RTC backup power failed and clock value is no longer valid. The user must reset this bit to 0
	to clear this condition.
CAL	Calibration Mode. When set to 1, a 512Hz square wave is output on the INT pin. When set to 0, the INT pin resumes
	normal operation. This bit defaults to 0 (disabled) on power up.

WWrite Enable. Setting the W bit to 1 freezes updates of the RTC registers and enables writes to RTC registers, Alarm registers, Calibration register, Interrupt register and Flags register. Setting the W bit to 0 causes the contents of the RTC registers to be transferred to the timekeeping counters if the time has been changed (a new base time is loaded). This bit defaults to 0 on power up.

RRead Time. Set R to 1 to captures the current time in holding registers so that clock updates are not seen during the reading process. Set R to 0 to enable the holding register to resume clock updates. This bit defaults to 0 on power up.

Document #: 001-52039 Rev. ** Page 20 of 23

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