Hardware Store Cycle, Soft Sequence Commands

STK17TA8

Hardware STORE Cycle

NO.	Symbols		Parameter	STK17TA8		Units	Notes
NO.	Standard	Alternate	Parameter	Min	Max	Units	Notes
	Standard	Alternate		Min	Max
31	tDELAY	tHLQZ	Hardware STORE to SRAM Disabled	1	70	μs	14
32	tHLHX		Hardware STORE Pulse Width	15		ns

NO.	Symbols	Parameter	STK17TA8		Units	Notes
	Standard		Min	Max
33	tSS	Soft Sequence Processing Time		70	μs	15,16
		Figure 13. Soft Sequence Commands
		33		33

Notes

14.On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow READ/WRITE cycles to compete.

15.This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.

16.Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.

Document #: 001-52039 Rev. **

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Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion Court Pinouts Pin Descriptions Symbol Parameter Commercial Industrial Units Min DC Electrical CharacteristicsRF SSOP-48 Package Thermal Characteristics Absolute Maximum Ratings AC Test Conditions Symbol Parameter Commercial Industrial Units Min MaxSymbol Parameter Max Units Conditions Capacitance RTC DC Characteristics Symbols Parameter STK17TA8-25 STK17TA8-45 Units Alt Min Max Sram Read Cycles #1 and #2 Sram Write Cycles #1 and #2 Symbols Parameter AutoStore/Power Up RecallUnits Standard Alternate Min Max Software-Controlled STORE/RECALL Cycle Hardware Store Cycle Soft Sequence CommandsHardware Store to Sram Disabled Hardware Store Pulse Width Mode Selection A16-A0 Mode Power Hardware Store HSB Operation Hardware Recall POWER-UPNvSRAM Operation AutoStore Operation Data Protection Low Average Active PowerSoftware Recall Noise Considerations RTC Operations Power Monitor Watchdog TimerAlarm Calibrating The Clock Flags Register InterruptsInterrupt Register RTC Register Register BCD Format Data Function / Range Register Map Detail 0x1FFF7 0x1FFF5 Alarm Day0x1FFF4 Alarm Hours 0x1FFF6 Interrupt 0x1FFF0 Flags 0x1FFF2 Alarm Seconds0x1FFF1 Real Time Clock Centuries 10s Centuries WDF Oscf CAL Ordering Information Ordering Codes Package Diagrams 51-85061 *C Document # 001-52039 Rev Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History