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Fujitsu MPG3XXXAH 5 Information to be read by IDENTIFY DEVICE command 3 of, X‘3FFF’, X‘01CA1E70’

Models: MPG3XXXAH

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Page 98

Table 5.5 Information to be read by IDENTIFY DEVICE command (3 of 6)

*1	Word 0: General configuration
	Bit 15: 0 = ATA device		0
	Bit 14-8: Vendor specific
	Bit 7: 1	= Removable media device	0
	Bit 6: 1	= not removable controller and/or device	1
	Bit 5-1: Vendor specific
	Bit 0: Reserved		0
*2	Number of Cylinders, *3 Number of Heads,

*11 Total number of user addressable sectors (LBA mode only.)

	MPF3102AH	MPF3153AH	MPF3204AH

*2		X‘3FFF’

*3		X‘10’

*11	X‘01316AF0’	X‘01CA1E70’	X‘0262D5E0’

*4 Word 10-19: Serial number; ASCII code (20 characters, right-justified)

*5 Word 23-26: Firmware revision; ASCII code (8 characters, Left-justified)

*6 Word 27-46: Model number;

ASCII code (40 characters, Left-justified), remainder filled with blank code (X'20') One of the following model numbers;

Fujitsu MPG3102AH

Fujitsu MPG3153AH

Fujitsu MPG3204AH

*7 Word 49:	Capabilities
Bit 15-14:	Reserved
Bit 13:	Standby timer value 0 = Standby timer values shall be managed by the device
Bit 12:	Reserved
Bit 11:	IORDY support	1=Supported
Bit 10:	IORDY inhibition	0=Disable inhibition
Bit 9:	LBA support	1=Supported
Bit 8:	DMA support	1=Supported
Bit 7-0:	Vendor specific

*8 Word 51: PIO data transfer mode

Bit 15-8: PIO data transfer mode X'02'=PIO mode 2

Bit 7-0: Vendor specific

*9	Word 53: Enable/disable setting of word 54-58, 64-70 and 88
	Bit 15-3:	Reserved
	Bit 2:	Enable/disable setting of word 88	1=Enable
	Bit 1:	Enable/disable setting of word 64-70	1=Enable
	Bit 0:	Enable/disable setting of word 54-58	1=Enable
*10	Word 59: Transfer sector count currently set by READ/WRITE MULTIPLE command
	Bit 15-9:	Reserved
	Bit 8:	Multiple sector transfer	1=Enable
	Bit 7-0:	Transfer sector count currently set by READ/WRITE MULTIPLE without
		interrupt supports 2, 4, 8 and 16 sectors.

C141-E112-01EN

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Fujitsu MPG3XXXAH manual 5 Information to be read by IDENTIFY DEVICE command 3 of, X‘3FFF’, X‘01CA1E70’

Contents

MPG3xxxAH DISK DRIVES PRODUCT MANUAL C141-E112-01EN7KHFRQWHQWVRIWKLVPDQXDOLVVXEMHFWWRFKDQJH ZLWKRXWSULRUQRWLFH 59,6,215&25C141-E112-01EN This page is intentionally left blank MAINTENANCE AND DIAGNOSIS REMOVAL AND REPLACEMENT PROCEDURE This manual MPG3xxxAH DISK DRIVES MAINTENANCE MANUAL C141-F047DEVICE OVERVIEW DEVICE CONFIGURATION INSTALLATION CONDITIONS MANUAL ORGANIZATION MPG3xxxAH DISK DRIVES PRODUCT MANUAL C141-E112This page is intentionally left blank INSTALLATION CONDITIONS PREFACEDEVICE CONFIGURATION ChapterConventions for Alert Messages LIABILITY EXCEPTION C141-E112-01ENThis page is intentionally left blank CHAPTER CONTENTSCHAPTER CHAPTERCHAPTER Command block registers Interface signalsSignal assignment on the connector Host CommandsCHAPTER TABLES Protocol for the command execution without data transfer Protocol for command abortWRITE SECTORS command protocol Multiword DMA data transfer timing modeTABLES This page is intentionally left blank 1.4 Environmental Specifications 1.5 Acoustic Noise CHAPTER 1 DEVICE OVERVIEW1.1 Features 1.2 Device Specifications 1.3 Power Requirements 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate1.1.2 Adaptability 1.1.3 InterfaceC141-E112-01EN 5 Error correction and retry by ECC6 Write cache 16.7 MB/s Max. burst PIO mode 4, burst DMA mode 1.2 Device Specifications 1.2.1 Specifications summarySpecifications 66.6 MB/s Max. burst ultra DMA modeTable 1.2 Model names and product numbers 1.3 Power Requirements1.2.2 Model and product number ModelTable 1.3 Current and power dissipation C141-E112-01ENFigure 1.1 Current fluctuation Typ. when power is turned on Table 1.5 Acoustic noise specification 1.4 Environmental SpecificationsEnvironmental specifications 1.5 Acoustic Noise1.7 Reliability Table 1.6 Shock and vibration specification1.6 Shock and Vibration 1.8 Error Rate 1.9 Media Defects2.1 Device Configuration CHAPTER 2 DEVICE CONFIGURATION2.1 Device Configuration 2.2 System Configuration Figure 2.1 Disk drive outerview3 Spindle motor 1 DiskMPG3102AH 1 disks MPG3153AH 2 disks MPG3204AH 2 disks 2 Head The disks are rotated by a direct drive Hall-less DC motor 4 ActuatorFigure 2.3 2 drives configuration 2.2 System Configuration 2.2.1 ATA interfaceFigure 2.2 1 drive system configuration 2.2.3 2 drives connection 2.2.2 1 drive connectionHA host adapter consists of address decoder, driver, and receiver. ATA is an abbreviation of AT attachment. The disk drive is conformed to the ATA-5 interface 3.4 Cable Connections 3.5 Jumper Settings 3.1 Dimensions CHAPTER 3 INSTALLATION CONDITIONS3.1 Dimensions 3.2 Handling Cautions 3.3 Mounting Figure 3.1 Dimensions C141-E112-01EN3.2.1 General notes 3.2.2 Installation3.2 Handling Cautions Figure 3.2 Handling cautions3.3 Mounting Figure 3.3 DirectionFigure 3.4 Limitation of side-mounting Figure 3.5 Mounting frame structureFigure 3.6 Surface temperature measurement points Table 3.1 Surface temperature measurement points and standard valuesFigure 3.7 Service area Power supply connector CN1 Mode Setting Pins ATA interface connector 3.4 Cable Connections 3.4.1 Device connector∙ Power supply connector CN1 ∙ ATA interface connector CN1 Figure 3.8 Connector locations3.4.3 Device connection 3.4.2 Cable connector specificationsTable 3.2 Cable connector specifications Figure 3.9 Cable connections3.4.5 System configuration for Ultra DMA 3.4.4 Power supply connector CN1Figure 3.10 Power supply connector pins CN1 Cable configuration Figure 3.12 Cable type detection using CBLID- signal Host sensing the condition of the CBLID- signal Interface Connector 3.5 Jumper Settings 3.5.1 Location of setting jumpersDC Power Connector Figure 3.14 Jumper locationFigure 3.16 Jumper setting of master or slave device 3.5.2 Factory default settingFigure 3.15 Factory default setting 3.5.3 Jumper configuration DC PowerFigure 3.19 Example 2 of Cable Select Figure 3.17 Jumper setting of Cable SelectFigure 3.18 Example 1 of Cable Select Slave Device 3 Special jumper settings a 2.1 GB clip Limit capacity to 2.1 GBMaster Device Cable Select4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/write Circuit CHAPTER 4 THEORY OF DEVICE OPERATION4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration 4.7 Servo ControlS p i n d l eA c t u a t o r 4.2.2 HeadFigure 4.1 Head structure S p i n d l eA c t u a t o r4.2.5 Air filter 4.2.3 Spindle4.2.4 Actuator 4.3 Circuit Configuration Page 4.4 Power-on Sequence Figure 4.3 Power-on operation sequence 4.5.1 Self-calibration contents 4.5 Self-calibration4.5.3 Command processing during self-calibration 4.6.2 Write circuit 4.6 Read/write Circuit4.6.1 Read/write preamplifier PreAMP 4.6.3 Read circuit 4.7 Servo Control 4.6.4 Synthesizer circuitTable 4.1 Transfer rate of each zone Servo burst capture Figure 4.4 Block diagram of servo control circuit4.7.1 Servo control circuit Figure 4.5 Physical sector servo configuration on disk surface Servoframe 96 servoframes per revolution3 A/D converter ADC 5 Power amplifier2 Servo burst capture circuit 4 D/A converter DAC4.7.2 Data-surface servo format 4.7.3 Servo frame formatFigure 4.6 96 servo frames in each track 4.7.4 Actuator motor control 4.7.5 Spindle motor control C141-E112-01EN 2 Acceleration mode3 Stable rotation mode 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands CHAPTERINTERFACE 5.4 Command Protocol 5.5 Ultra DMA feature set 5.6 TimingTable 5.1 Interface signals 5.1 Physical Interface 5.1.1 Interface signalsTable 5.1 shows the interface signals C141-E112-01EN5.1.2 Signal assignment on the connector Table 5.2 Signal assignment on the interface connectorsignal register access Read or Write when the device is not ready to respond device is ready to receive Ultra DMA data out bursts. The device may5.2 Logical Interface 5.2.1 I/O registersTable 5.3 I/O registers 5.2.2 Command block registers 3 Features register X1F1 Diagnostic code X01 No Error Detected X02 HDC Register Compare ErrorX03 Data Buffer Compare Error X05 ROM Sum Check Error X80 Device 1 slave device FailedBit 3 HS3 CHS mode head address 3 23. LBA bit The contents of this register indicate the device and the head numberL. 0 for CHS mode and 1 for LBA mode Bit 2 HS2 CHS mode head address 3 22. LBA bitC141-E112-01EN 9 Status register X1F7DRDY Always 10 Command register X1F7Always C141-E112-01EN5.3 Host Commands 5.2.3 Control block registers5.3.1 Command code and parameters Table 5.4 Command code and parameters 1 ofTable 5.4 Command code and parameters 2 of 5.3.2 Command descriptions Transfer sector count1F7 HCM At command issuance I/O registers setting contents1 READ SECTORS X20 or 1F6 HDH1F7 HST At command completion I/O registers contents to be readError information Status informationFigure 5.1 Execution example of READ MULTIPLE command 1 Multiword DMA transfer mode ∙ The data transfer starts at the timing of DMARQ signal assertionIn LBA mode 2 Ultra DMA transfer modeAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 1F7 HSTAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 1F7 HST1F7 HST At command completion I/O registers contents to be readError information Status informationError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read ∙ The data transfer starts at the timing of DMARQ signal assertionAt command issuance I/O registers setting contents 1 Multiword DMA transfer mode2 Ultra DMA transfer mode R = 0 or At command completion I/O registers contents to be readThis command can be issued in the LBA mode At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 10 SEEK X7x, x X0 to XFAt command completion I/O registers contents to be read In LBA modeAt command issuance I/O registers setting contents Error InformationNumber of cylinders Table 5.5 Information to be read by IDENTIFY DEVICE command 1 ofX‘045A’ Number of sectors per trackTable 5.5 Information to be read by IDENTIFY DEVICE command 2 of X‘00’X‘01CA1E70’ Table 5.5 Information to be read by IDENTIFY DEVICE command 3 ofX‘3FFF’ Transfer sector count currently set by READ/WRITE MULTIPLE withoutInformation to be read by IDENTIFY DEVICE command 4 of C141-E112-01ENTable 5.5 Information to be read by IDENTIFY DEVICE command 5 of = SET MAX security extension enabled by SET MAX SET PASSWORDTable 5.5 Information to be read by IDENTIFY DEVICE command 6 of C141-E112-01ENError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 14 SET FEATURES XEFTable 5.6 Features register values and settable modes X‘AA’At command completion I/O registers contents to be read At command issuance I/O registers setting contentsxx or transfer mode Error informationLevel 15 SET MULTIPLE MODE XC6Automatic management levels Sector Count valueError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 16 EXECUTE DEVICE DIAGNOSTICTable 5.7 Diagnostic code R = 0 or At command completion I/O registers contents to be read The READ LONG command supports only single sector operationAt command issuance I/O registers setting contents Error informationError information At command issuance I/O registers setting contentsR = 0 or At command completion I/O registers contents to be read At command issuance I/O registers setting contentsAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information At command completion I/O registers contents to be readAt command issuance I/O registers setting contents Point of timerDisable of timer Period of timerAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information At command completion I/O registers contents to be readAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsPeriod of timer Error informationError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read This command is the only way to make the device enter the sleep mode27 CHECK POWER MODE X98 or XE5 At command completion I/O registers contents to be readError information The host checks the power mode of the device with this commandError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 1F7 HCMTable 5.8 Features Register values subcommands and functions At command completion I-O registers setting contents At command issuance I-O registers setting contentsSubcommand Error informationTable 5.9 Format of device attribute value data Table 5.10 Format of insurance failure threshold value data Power-on time Read error rateSeek error rate Number of power-on-power-off timesBits 2 to 15 Reserved bits ∙ Check sum ∙ Raw attribute value Raw attributes data is retained∙ Failure prediction capability flag ∙ Insurance failure thresholdAt command completion I/O registers contents to be read NOTE This command may take longer than 30 s to completeAt command issuance I/O registers setting contents Error informationTable 5.11 Contents of security password Error information At command issuance I-O registers setting contentsAt command completion I-O registers setting contents 1F7 HCMError information At command issuance I-O registers setting contentsAt command completion I-O registers setting contents 1F7 HCMError information At command issuance I-O registers setting contentsAt command completion I-O registers setting contents ∙ SECURITY SET PASSWORD ∙ SECURITY UNLOCK ∙ SECURITY DISABLE PASSWORD∙ WRITE DMA At command issuance I-O registers setting contents SECURITY DISABLE PASSWORDSECURITY SET PASSWORD At command completion I-O registers setting contentsbetween combination of Identifier and Security level, and Table 5.12 Contents of SECURITY SET PASSWORD dataRelationship operation of the lock functionError information At command issuance I-O registers setting contentsAt command completion I-O registers setting contents 35 SECURITY UNLOCK F2h This command cancels LOCKED MODEError information At command issuance I-O registers setting contentsAt command completion I-O registers setting contents 1F7 HCMError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 36-2 SET MAX SET PASSWORD F9SET MAX SET PASSWORD data content At command completion I/O registers contents to be readError information ContentError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 36-4 SET MAX UNLOCK F9At command completion I/O registers contents to be read ∙ SET MAX ADDRESS ∙ SET MAX SET PASSWORD ∙ SET MAX LOCK∙ SET MAX UNLOCK At command issuance I/O registers setting contents Error information1F7HST At command completion I/O registers contents to be readError information Status informationICRC 5.3.3 Error postingTable 5.14 Command code and parameters 5.4 Command Protocol 5.4.1 Data transferring commands from device to hostFigure 5.2 Read Sectors command protocol Figure 5.3 Protocol for command abort 5.4.2 Data transferring commands from host to deviceExpanded Figure 5.4 WRITE SECTORS command protocolStatus read 5.4.3 Commands without data transfer Figure 5.5 Protocol for the command execution without data transfer5.4.4 Other commands 5.4.5 DMA data transfer commandsFigure 5.6 Normal DMA data transfer 5.5 Ultra DMA feature set 5.5.1 Overview 5.5.3.1 Initiating an Ultra DMA data in burst 5.5.2 Phases of operation5.5.3 Ultra DMA data in commands 5.5.3.3 Pausing an Ultra DMA data in burst 5.5.3.2 The data in transfer5.5.3.4 Terminating an Ultra DMA data in burst b Host terminating an Ultra DMA data in burst C141-E112-01EN5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst5.5.4.3 Pausing an Ultra DMA data out burst 5.5.4.2 The data out transfer5.5.4.4 Terminating an Ultra DMA data out burst b Device terminating an Ultra DMA data out burst C141-E112-01EN5.5.5 Ultra DMA CRC rules Figure 5.7 Ultra DMA termination with pull-up or pull-down 5.5.6 Series termination required for Ultra DMATable 5.15 Recommended series termination for Ultra DMA 5.6 Timing 5.6.1 PIO data transfer Figure 5.8 PIO data transfer timingFigure 5.9 Multiword DMA data transfer timing mode 5.6.2 Multiword data transferDMARQ 5.6.3 Ultra DMA data transfer5.6.3.1 Initiating an Ultra DMA data in burst device5.6.3.2 Ultra DMA data burst timing requirements Table 5.16 Ultra DMA data burst timing requirements 1 ofTable 5.16 Ultra DMA data burst timing requirements 2 of tDHIC Table 5.17 Ultra DMA sender and recipient timing requirementstDSIC tDVSICDD150 at device DSTROBE at host 5.6.3.3 Sustained Ultra DMA data in burstDSTROBE at device DD150 at hosttRFS 5.6.3.4 Host pausing an Ultra DMA data in burstFigure 5.12 Host pausing an Ultra DMA data in burst DMACK- host STOP host HDMARDY- host DSTROBE device DD150 5.6.3.5 Device terminating an Ultra DMA data in burstDMARQ device DA0, DA1, DA2 CS0-, CS1host 5.6.3.6 Host terminating an Ultra DMA data in burstDMACK STOPDD150 host 5.6.3.7 Initiating an Ultra DMA data out burstFigure 5.15 Initiating an Ultra DMA data out burst HSTROBE at device DD150 at device 5.6.3.8 Sustained Ultra DMA data out burstHSTROBE at host DD150 at host Figure 5.16 Sustained Ultra DMA data out burst5.6.3.9 Device pausing an Ultra DMA data out burst Figure 5.17 Device pausing an Ultra DMA data out bursttIORDYZ 5.6.3.10 Host terminating an Ultra DMA data out burstFigure 5.18 Host terminating an Ultra DMA data out burst 5.6.3.11 Device terminating an Ultra DMA data in burst Figure 5.19 Device terminating an Ultra DMA data out burst5.6.4 Power-on and reset Figure 5.20 Power-on Reset Timing6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache OPERATIONS6.1 Device Response to the Reset 6.2 Address Translation 6.6 Write Cache 6.1 Device Response to the Reset6.1.1 Response to power-on Figure 6.1 Response to power-on6.1.2 Response to hardware reset Figure 6.2 Response to hardware reset6.1.3 Response to software reset Figure 6.3 Response to software reset6.1.4 Response to diagnostic command Figure 6.4 Response to diagnostic command6.2 Address Translation 6.2.1 Default parametersDefault parameters Figure 6.5 Address translation example in CHS mode 6.2.2 Logical addressFigure 6.6 Address translation example in LBA mode 6.3 Power Save 6.3.1 Power save mode∙ A command with Seek or Write or Read is issued 2 Idle mode 1 Active modeA device enters the active mode under the following conditions Reset hardware or software IDLE command IDLE IMMEDIATE command6.3.2 Power commands 6.4 Defect ManagementFigure 6.7 Sector slip processing 6.4.1 Spare area6.4.2 Alternating defective sectors DefectiveFigure 6.8 Alternate cylinder assignment 6.5 Read-Ahead Cache 6.5.1 Data buffer configurationFigure 6.9 Data buffer configuration 6.5.2 Caching operation 6.5.3 Usage of read segment Requested data Read-ahead data b. Sequential hitHAP Completion of transferring requested data Hit data3 Full hit hit all Last position at previous read commandDAP Last position at previous read command HAP set to hit position for data transferRequested data to be transferred Partially hit dataLack data HAP stopped6.6 Write Cache When the write cache function is enabled, the transferred data from the host by the WRITE SECTORS is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function UDQNIXUWHU5LQJ0QFKHQ*50$1 RXQJXQJ3R*X6HRXO5HSXEOLFRI.25$RQJZDON5RDG6WRFNOH\3DUN8EULGJH XQJ+DQV9lJ66ROOHQWXUD618-,768/,0,7 5HDGHU&RPPHQWRUP