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Fujitsu MPG3XXXAH STANDBY X96 or XE2, At command issuance I/O registers setting contents, 1F7 HCM

Models: MPG3XXXAH

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(24)STANDBY (X'96' or X'E2')

(24)STANDBY (X'96' or X'E2')

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode. If the device has already spun down, the spin-down sequence is not implemented.

If the contents of the Sector Count register is other than 0, the automatic power-down function is enabled and the timer starts countdown when the device returns to idle mode.

When the timer value reaches 0 (passed a specified time), the device enters the standby mode. If the contents of the Sector Count register is 0, the automatic power-down function is disabled.

Under the standby mode, the spindle motor is stopped. Thus, when the command involving a seek such as the READ SECTOR(s) command is received, the device processes the command after driving the spindle motor.

At command issuance (I/O registers setting contents)

1F7H(CM)					X'96' or X'E2'

1F6H(DH)	×	×	×		DV		xx

1F5H(CH)					xx
1F4H(CL)					xx
1F3H(SN)					xx
1F2H(SC)				Period of timer
1F1H(FR)					xx

At command completion (I/O registers contents to be read)

1F7H(ST)				Status information

1F6H(DH)	×	×	×		DV		xx

1F5H(CH)					xx
1F4H(CL)					xx
1F3H(SN)					xx
1F2H(SC)					xx
1F1H(ER)				Error information

(25)STANDBY IMMEDIATE (X'94' or X'E0')

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. This command does not support the automatic power-down sequence.

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C141-E112-01EN

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Fujitsu MPG3XXXAH manual STANDBY X96 or XE2, At command issuance I/O registers setting contents, 1F7 HCM, 1F6 HDH, 1F5 HCH

Contents

C141-E112-01EN MPG3xxxAH DISK DRIVES PRODUCT MANUAL7KHFRQWHQWVRIWKLVPDQXDOLVVXEMHFWWRFKDQJH ZLWKRXWSULRUQRWLFH 59,6,215&25C141-E112-01EN This page is intentionally left blank DEVICE OVERVIEW DEVICE CONFIGURATION INSTALLATION CONDITIONS This manual MPG3xxxAH DISK DRIVES MAINTENANCE MANUAL C141-F047MAINTENANCE AND DIAGNOSIS REMOVAL AND REPLACEMENT PROCEDURE MANUAL ORGANIZATION MPG3xxxAH DISK DRIVES PRODUCT MANUAL C141-E112This page is intentionally left blank DEVICE CONFIGURATION PREFACEINSTALLATION CONDITIONS ChapterConventions for Alert Messages C141-E112-01EN LIABILITY EXCEPTIONThis page is intentionally left blank CHAPTER CONTENTSCHAPTER CHAPTERCHAPTER Signal assignment on the connector Interface signalsCommand block registers Host CommandsCHAPTER TABLES WRITE SECTORS command protocol Protocol for command abortProtocol for the command execution without data transfer Multiword DMA data transfer timing modeTABLES This page is intentionally left blank 1.1 Features 1.2 Device Specifications 1.3 Power Requirements CHAPTER 1 DEVICE OVERVIEW1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate1.1.3 Interface 1.1.2 AdaptabilityC141-E112-01EN 5 Error correction and retry by ECC6 Write cache Specifications 1.2 Device Specifications 1.2.1 Specifications summary16.7 MB/s Max. burst PIO mode 4, burst DMA mode 66.6 MB/s Max. burst ultra DMA mode1.2.2 Model and product number 1.3 Power RequirementsTable 1.2 Model names and product numbers ModelC141-E112-01EN Table 1.3 Current and power dissipationFigure 1.1 Current fluctuation Typ. when power is turned on Environmental specifications 1.4 Environmental SpecificationsTable 1.5 Acoustic noise specification 1.5 Acoustic Noise1.7 Reliability Table 1.6 Shock and vibration specification1.6 Shock and Vibration 1.9 Media Defects 1.8 Error Rate2.1 Device Configuration 2.2 System Configuration CHAPTER 2 DEVICE CONFIGURATION2.1 Device Configuration Figure 2.1 Disk drive outerviewMPG3102AH 1 disks MPG3153AH 2 disks MPG3204AH 2 disks 2 Head 1 Disk3 Spindle motor The disks are rotated by a direct drive Hall-less DC motor 4 ActuatorFigure 2.2 1 drive system configuration 2.2.3 2 drives connection 2.2 System Configuration 2.2.1 ATA interfaceFigure 2.3 2 drives configuration 2.2.2 1 drive connectionHA host adapter consists of address decoder, driver, and receiver. ATA is an abbreviation of AT attachment. The disk drive is conformed to the ATA-5 interface 3.4 Cable Connections 3.5 Jumper Settings 3.1 Dimensions CHAPTER 3 INSTALLATION CONDITIONS3.1 Dimensions 3.2 Handling Cautions 3.3 Mounting C141-E112-01EN Figure 3.1 Dimensions3.2 Handling Cautions 3.2.2 Installation3.2.1 General notes Figure 3.2 Handling cautionsFigure 3.3 Direction 3.3 MountingFigure 3.5 Mounting frame structure Figure 3.4 Limitation of side-mountingTable 3.1 Surface temperature measurement points and standard values Figure 3.6 Surface temperature measurement pointsFigure 3.7 Service area ∙ Power supply connector CN1 ∙ ATA interface connector CN1 3.4 Cable Connections 3.4.1 Device connectorPower supply connector CN1 Mode Setting Pins ATA interface connector Figure 3.8 Connector locationsTable 3.2 Cable connector specifications 3.4.2 Cable connector specifications3.4.3 Device connection Figure 3.9 Cable connections3.4.5 System configuration for Ultra DMA 3.4.4 Power supply connector CN1Figure 3.10 Power supply connector pins CN1 Cable configuration Figure 3.12 Cable type detection using CBLID- signal Host sensing the condition of the CBLID- signal DC Power Connector 3.5 Jumper Settings 3.5.1 Location of setting jumpersInterface Connector Figure 3.14 Jumper locationFigure 3.15 Factory default setting 3.5.3 Jumper configuration 3.5.2 Factory default settingFigure 3.16 Jumper setting of master or slave device DC PowerFigure 3.19 Example 2 of Cable Select Figure 3.17 Jumper setting of Cable SelectFigure 3.18 Example 1 of Cable Select Master Device 3 Special jumper settings a 2.1 GB clip Limit capacity to 2.1 GBSlave Device Cable Select4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration CHAPTER 4 THEORY OF DEVICE OPERATION4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/write Circuit 4.7 Servo ControlFigure 4.1 Head structure 4.2.2 HeadS p i n d l eA c t u a t o r S p i n d l eA c t u a t o r4.2.5 Air filter 4.2.3 Spindle4.2.4 Actuator 4.3 Circuit Configuration Page 4.4 Power-on Sequence Figure 4.3 Power-on operation sequence 4.5 Self-calibration 4.5.1 Self-calibration contents4.5.3 Command processing during self-calibration 4.6.2 Write circuit 4.6 Read/write Circuit4.6.1 Read/write preamplifier PreAMP 4.6.3 Read circuit 4.7 Servo Control 4.6.4 Synthesizer circuitTable 4.1 Transfer rate of each zone Servo burst capture Figure 4.4 Block diagram of servo control circuit4.7.1 Servo control circuit Servoframe 96 servoframes per revolution Figure 4.5 Physical sector servo configuration on disk surface2 Servo burst capture circuit 5 Power amplifier3 A/D converter ADC 4 D/A converter DAC4.7.3 Servo frame format 4.7.2 Data-surface servo formatFigure 4.6 96 servo frames in each track 4.7.4 Actuator motor control 4.7.5 Spindle motor control C141-E112-01EN 2 Acceleration mode3 Stable rotation mode INTERFACE CHAPTER5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Ultra DMA feature set 5.6 TimingTable 5.1 shows the interface signals 5.1 Physical Interface 5.1.1 Interface signalsTable 5.1 Interface signals C141-E112-01ENTable 5.2 Signal assignment on the interface connector 5.1.2 Signal assignment on the connectorsignal device is ready to receive Ultra DMA data out bursts. The device may register access Read or Write when the device is not ready to respond5.2.1 I/O registers 5.2 Logical InterfaceTable 5.3 I/O registers 5.2.2 Command block registers X03 Data Buffer Compare Error X05 ROM Sum Check Error Diagnostic code X01 No Error Detected X02 HDC Register Compare Error3 Features register X1F1 X80 Device 1 slave device FailedL. 0 for CHS mode and 1 for LBA mode The contents of this register indicate the device and the head numberBit 3 HS3 CHS mode head address 3 23. LBA bit Bit 2 HS2 CHS mode head address 3 22. LBA bitC141-E112-01EN 9 Status register X1F7DRDY Always 10 Command register X1F7Always C141-E112-01EN5.2.3 Control block registers 5.3 Host CommandsTable 5.4 Command code and parameters 1 of 5.3.1 Command code and parametersTable 5.4 Command code and parameters 2 of Transfer sector count 5.3.2 Command descriptions1 READ SECTORS X20 or At command issuance I/O registers setting contents1F7 HCM 1F6 HDHError information At command completion I/O registers contents to be read1F7 HST Status informationFigure 5.1 Execution example of READ MULTIPLE command In LBA mode ∙ The data transfer starts at the timing of DMARQ signal assertion1 Multiword DMA transfer mode 2 Ultra DMA transfer modeError information At command completion I/O registers contents to be readAt command issuance I/O registers setting contents 1F7 HSTError information At command completion I/O registers contents to be readAt command issuance I/O registers setting contents 1F7 HSTError information At command completion I/O registers contents to be read1F7 HST Status informationAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information ∙ The data transfer starts at the timing of DMARQ signal assertion2 Ultra DMA transfer mode 1 Multiword DMA transfer modeAt command issuance I/O registers setting contents R = 0 or At command completion I/O registers contents to be readError information At command completion I/O registers contents to be readThis command can be issued in the LBA mode At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information 10 SEEK X7x, x X0 to XFAt command issuance I/O registers setting contents In LBA modeAt command completion I/O registers contents to be read Error InformationX‘045A’ Table 5.5 Information to be read by IDENTIFY DEVICE command 1 ofNumber of cylinders Number of sectors per trackX‘00’ Table 5.5 Information to be read by IDENTIFY DEVICE command 2 ofX‘3FFF’ Table 5.5 Information to be read by IDENTIFY DEVICE command 3 ofX‘01CA1E70’ Transfer sector count currently set by READ/WRITE MULTIPLE withoutC141-E112-01EN Information to be read by IDENTIFY DEVICE command 4 of= SET MAX security extension enabled by SET MAX SET PASSWORD Table 5.5 Information to be read by IDENTIFY DEVICE command 5 ofC141-E112-01EN Table 5.5 Information to be read by IDENTIFY DEVICE command 6 ofAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information 14 SET FEATURES XEFX‘AA’ Table 5.6 Features register values and settable modesxx or transfer mode At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationAutomatic management levels 15 SET MULTIPLE MODE XC6Level Sector Count valueAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information 16 EXECUTE DEVICE DIAGNOSTICTable 5.7 Diagnostic code At command issuance I/O registers setting contents The READ LONG command supports only single sector operationR = 0 or At command completion I/O registers contents to be read Error informationR = 0 or At command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information At command issuance I/O registers setting contentsError information At command completion I/O registers contents to be readAt command issuance I/O registers setting contents At command completion I/O registers contents to be readDisable of timer Point of timerAt command issuance I/O registers setting contents Period of timerError information At command completion I/O registers contents to be readAt command issuance I/O registers setting contents At command completion I/O registers contents to be readPeriod of timer At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information This command is the only way to make the device enter the sleep modeError information At command completion I/O registers contents to be read27 CHECK POWER MODE X98 or XE5 The host checks the power mode of the device with this commandAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information 1F7 HCMTable 5.8 Features Register values subcommands and functions Subcommand At command issuance I-O registers setting contentsAt command completion I-O registers setting contents Error informationTable 5.9 Format of device attribute value data Table 5.10 Format of insurance failure threshold value data Seek error rate Read error ratePower-on time Number of power-on-power-off times∙ Failure prediction capability flag ∙ Raw attribute value Raw attributes data is retainedBits 2 to 15 Reserved bits ∙ Check sum ∙ Insurance failure thresholdAt command issuance I/O registers setting contents NOTE This command may take longer than 30 s to completeAt command completion I/O registers contents to be read Error informationTable 5.11 Contents of security password At command completion I-O registers setting contents At command issuance I-O registers setting contentsError information 1F7 HCMAt command completion I-O registers setting contents At command issuance I-O registers setting contentsError information 1F7 HCMAt command completion I-O registers setting contents At command issuance I-O registers setting contentsError information ∙ SECURITY SET PASSWORD ∙ SECURITY UNLOCK ∙ SECURITY DISABLE PASSWORDSECURITY SET PASSWORD SECURITY DISABLE PASSWORD∙ WRITE DMA At command issuance I-O registers setting contents At command completion I-O registers setting contentsRelationship Table 5.12 Contents of SECURITY SET PASSWORD databetween combination of Identifier and Security level, and operation of the lock functionAt command completion I-O registers setting contents At command issuance I-O registers setting contentsError information 35 SECURITY UNLOCK F2h This command cancels LOCKED MODEAt command completion I-O registers setting contents At command issuance I-O registers setting contentsError information 1F7 HCMAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information 36-2 SET MAX SET PASSWORD F9Error information At command completion I/O registers contents to be readSET MAX SET PASSWORD data content ContentAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information 36-4 SET MAX UNLOCK F9∙ SET MAX UNLOCK At command issuance I/O registers setting contents ∙ SET MAX ADDRESS ∙ SET MAX SET PASSWORD ∙ SET MAX LOCKAt command completion I/O registers contents to be read Error informationError information At command completion I/O registers contents to be read1F7HST Status informationICRC 5.3.3 Error postingTable 5.14 Command code and parameters 5.4.1 Data transferring commands from device to host 5.4 Command ProtocolFigure 5.2 Read Sectors command protocol 5.4.2 Data transferring commands from host to device Figure 5.3 Protocol for command abortExpanded Figure 5.4 WRITE SECTORS command protocolStatus read Figure 5.5 Protocol for the command execution without data transfer 5.4.3 Commands without data transfer5.4.5 DMA data transfer commands 5.4.4 Other commandsFigure 5.6 Normal DMA data transfer 5.5 Ultra DMA feature set 5.5.1 Overview 5.5.3.1 Initiating an Ultra DMA data in burst 5.5.2 Phases of operation5.5.3 Ultra DMA data in commands 5.5.3.2 The data in transfer 5.5.3.3 Pausing an Ultra DMA data in burst5.5.3.4 Terminating an Ultra DMA data in burst C141-E112-01EN b Host terminating an Ultra DMA data in burst5.5.4.1 Initiating an Ultra DMA data out burst 5.5.4 Ultra DMA data out commands5.5.4.2 The data out transfer 5.5.4.3 Pausing an Ultra DMA data out burst5.5.4.4 Terminating an Ultra DMA data out burst C141-E112-01EN b Device terminating an Ultra DMA data out burst5.5.5 Ultra DMA CRC rules Figure 5.7 Ultra DMA termination with pull-up or pull-down 5.5.6 Series termination required for Ultra DMATable 5.15 Recommended series termination for Ultra DMA Figure 5.8 PIO data transfer timing 5.6 Timing 5.6.1 PIO data transfer5.6.2 Multiword data transfer Figure 5.9 Multiword DMA data transfer timing mode5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3 Ultra DMA data transferDMARQ deviceTable 5.16 Ultra DMA data burst timing requirements 1 of 5.6.3.2 Ultra DMA data burst timing requirementsTable 5.16 Ultra DMA data burst timing requirements 2 of tDSIC Table 5.17 Ultra DMA sender and recipient timing requirementstDHIC tDVSICDSTROBE at device 5.6.3.3 Sustained Ultra DMA data in burstDD150 at device DSTROBE at host DD150 at hosttRFS 5.6.3.4 Host pausing an Ultra DMA data in burstFigure 5.12 Host pausing an Ultra DMA data in burst DMARQ device 5.6.3.5 Device terminating an Ultra DMA data in burstDMACK- host STOP host HDMARDY- host DSTROBE device DD150 DA0, DA1, DA2 CS0-, CS1DMACK 5.6.3.6 Host terminating an Ultra DMA data in bursthost STOPDD150 host 5.6.3.7 Initiating an Ultra DMA data out burstFigure 5.15 Initiating an Ultra DMA data out burst HSTROBE at host DD150 at host 5.6.3.8 Sustained Ultra DMA data out burstHSTROBE at device DD150 at device Figure 5.16 Sustained Ultra DMA data out burstFigure 5.17 Device pausing an Ultra DMA data out burst 5.6.3.9 Device pausing an Ultra DMA data out bursttIORDYZ 5.6.3.10 Host terminating an Ultra DMA data out burstFigure 5.18 Host terminating an Ultra DMA data out burst Figure 5.19 Device terminating an Ultra DMA data out burst 5.6.3.11 Device terminating an Ultra DMA data in burstFigure 5.20 Power-on Reset Timing 5.6.4 Power-on and reset6.1 Device Response to the Reset 6.2 Address Translation OPERATIONS6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache 6.6 Write Cache 6.1 Device Response to the ResetFigure 6.1 Response to power-on 6.1.1 Response to power-onFigure 6.2 Response to hardware reset 6.1.2 Response to hardware resetFigure 6.3 Response to software reset 6.1.3 Response to software resetFigure 6.4 Response to diagnostic command 6.1.4 Response to diagnostic command6.2 Address Translation 6.2.1 Default parametersDefault parameters 6.2.2 Logical address Figure 6.5 Address translation example in CHS mode6.3.1 Power save mode Figure 6.6 Address translation example in LBA mode 6.3 Power SaveA device enters the active mode under the following conditions 1 Active mode∙ A command with Seek or Write or Read is issued 2 Idle mode Reset hardware or software IDLE command IDLE IMMEDIATE command6.4 Defect Management 6.3.2 Power commands6.4.2 Alternating defective sectors 6.4.1 Spare areaFigure 6.7 Sector slip processing DefectiveFigure 6.8 Alternate cylinder assignment 6.5 Read-Ahead Cache 6.5.1 Data buffer configurationFigure 6.9 Data buffer configuration 6.5.2 Caching operation 6.5.3 Usage of read segment Requested data HAP Completion of transferring requested data b. Sequential hitRead-ahead data Hit dataDAP Last position at previous read command Last position at previous read command3 Full hit hit all HAP set to hit position for data transferLack data Partially hit dataRequested data to be transferred HAP stopped6.6 Write Cache When the write cache function is enabled, the transferred data from the host by the WRITE SECTORS is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function RQJZDON5RDG6WRFNOH\3DUN8EULGJH RXQJXQJ3R*X6HRXO5HSXEOLFRI.25$UDQNIXUWHU5LQJ0QFKHQ*50$1 XQJ+DQV9lJ66ROOHQWXUD615HDGHU&RPPHQWRUP 8-,768/,0,7