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Fujitsu MPG3XXXAH At command issuance I/O registers setting contents, 1F7 HCM, 1F6 HDH, 1F5 HCH

Models: MPG3XXXAH

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00H

The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual requests.

At command issuance (I/O registers setting contents)

1F7H(CM)	1	1	0	0	0	1	0	1

1F6H(DH)	×	L	×	DV	Start head No. /LBA [MSB]

1F5H(CH)		Start cylinder No. [MSB] / LBA
1F4H(CL)		Start cylinder No. [LSB]				/ LBA
1F3H(SN)		Start sector No.				/ LBA [LSB]
1F2H(SC)			Transfer sector count
1F1H(FR)				xx

At command completion (I/O registers contents to be read)

1F7H(ST)				Status information

1F6H(DH)	×	L	×		DV		End head No. /LBA [MSB]

1F5H(CH)		End cylinder No. [MSB]						/ LBA
1F4H(CL)		End cylinder No. [LSB]						/ LBA
1F3H(SN)		End sector No.						/ LBA [LSB]
1F2H(SC)					00H
1F1H(ER)				Error information

Note:

When the command terminates due to error, only the DV bit and the error information field are valid.

(7)WRITE DMA (X'CA' or X'CB')

This command operates similarly to the WRITE SECTOR(S) command except for following events.

∙The data transfer starts at the timing of DMARQ signal assertion.

∙The device controls the assertion or negation timing of the DMARQ signal.

∙The device posts a status as the result of command execution only once at completion of the data transfer.

When an error, such as an unrecoverable medium error, that the command execution cannot be continued is detected, the data transfer is stopped without transferring data of sectors after the erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the host system. The format of the error information is the same as the WRITE SECTOR(S) command.

A host system can be select the following transfer mode using the SET FEATURES command.

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C141-E112-01EN

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Fujitsu MPG3XXXAH At command issuance I/O registers setting contents, 1F7 HCM, 1F6 HDH, Start head No. /LBA MSB, 1F5 HCH

Contents

C141-E112-01EN MPG3xxxAH DISK DRIVES PRODUCT MANUALC141-E112-01EN 59,6,215&257KHFRQWHQWVRIWKLVPDQXDOLVVXEMHFWWRFKDQJH ZLWKRXWSULRUQRWLFH This page is intentionally left blank MANUAL ORGANIZATION MPG3xxxAH DISK DRIVES PRODUCT MANUAL C141-E112 This manual MPG3xxxAH DISK DRIVES MAINTENANCE MANUAL C141-F047DEVICE OVERVIEW DEVICE CONFIGURATION INSTALLATION CONDITIONS MAINTENANCE AND DIAGNOSIS REMOVAL AND REPLACEMENT PROCEDUREThis page is intentionally left blank Chapter PREFACEDEVICE CONFIGURATION INSTALLATION CONDITIONSConventions for Alert Messages C141-E112-01EN LIABILITY EXCEPTIONThis page is intentionally left blank CHAPTER CONTENTSCHAPTER CHAPTERCHAPTER Host Commands Interface signalsSignal assignment on the connector Command block registersCHAPTER TABLES Multiword DMA data transfer timing mode Protocol for command abortWRITE SECTORS command protocol Protocol for the command execution without data transferTABLES This page is intentionally left blank 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate CHAPTER 1 DEVICE OVERVIEW1.1 Features 1.2 Device Specifications 1.3 Power Requirements 1.4 Environmental Specifications 1.5 Acoustic Noise1.1.3 Interface 1.1.2 Adaptability6 Write cache 5 Error correction and retry by ECCC141-E112-01EN 66.6 MB/s Max. burst ultra DMA mode 1.2 Device Specifications 1.2.1 Specifications summarySpecifications 16.7 MB/s Max. burst PIO mode 4, burst DMA modeModel 1.3 Power Requirements1.2.2 Model and product number Table 1.2 Model names and product numbersC141-E112-01EN Table 1.3 Current and power dissipationFigure 1.1 Current fluctuation Typ. when power is turned on 1.5 Acoustic Noise 1.4 Environmental SpecificationsEnvironmental specifications Table 1.5 Acoustic noise specification1.6 Shock and Vibration Table 1.6 Shock and vibration specification1.7 Reliability 1.9 Media Defects 1.8 Error RateFigure 2.1 Disk drive outerview CHAPTER 2 DEVICE CONFIGURATION2.1 Device Configuration 2.2 System Configuration 2.1 Device ConfigurationThe disks are rotated by a direct drive Hall-less DC motor 4 Actuator 1 DiskMPG3102AH 1 disks MPG3153AH 2 disks MPG3204AH 2 disks 2 Head 3 Spindle motor2.2.2 1 drive connection 2.2 System Configuration 2.2.1 ATA interfaceFigure 2.2 1 drive system configuration 2.2.3 2 drives connection Figure 2.3 2 drives configurationHA host adapter consists of address decoder, driver, and receiver. ATA is an abbreviation of AT attachment. The disk drive is conformed to the ATA-5 interface 3.1 Dimensions 3.2 Handling Cautions 3.3 Mounting CHAPTER 3 INSTALLATION CONDITIONS3.4 Cable Connections 3.5 Jumper Settings 3.1 Dimensions C141-E112-01EN Figure 3.1 DimensionsFigure 3.2 Handling cautions 3.2.2 Installation3.2 Handling Cautions 3.2.1 General notesFigure 3.3 Direction 3.3 MountingFigure 3.5 Mounting frame structure Figure 3.4 Limitation of side-mountingTable 3.1 Surface temperature measurement points and standard values Figure 3.6 Surface temperature measurement pointsFigure 3.7 Service area Figure 3.8 Connector locations 3.4 Cable Connections 3.4.1 Device connector∙ Power supply connector CN1 ∙ ATA interface connector CN1 Power supply connector CN1 Mode Setting Pins ATA interface connectorFigure 3.9 Cable connections 3.4.2 Cable connector specificationsTable 3.2 Cable connector specifications 3.4.3 Device connectionFigure 3.10 Power supply connector pins CN1 3.4.4 Power supply connector CN13.4.5 System configuration for Ultra DMA Cable configuration Figure 3.12 Cable type detection using CBLID- signal Host sensing the condition of the CBLID- signal Figure 3.14 Jumper location 3.5 Jumper Settings 3.5.1 Location of setting jumpersDC Power Connector Interface ConnectorDC Power 3.5.2 Factory default settingFigure 3.15 Factory default setting 3.5.3 Jumper configuration Figure 3.16 Jumper setting of master or slave deviceFigure 3.18 Example 1 of Cable Select Figure 3.17 Jumper setting of Cable SelectFigure 3.19 Example 2 of Cable Select Cable Select 3 Special jumper settings a 2.1 GB clip Limit capacity to 2.1 GBMaster Device Slave Device4.7 Servo Control CHAPTER 4 THEORY OF DEVICE OPERATION4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration 4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/write CircuitS p i n d l eA c t u a t o r 4.2.2 HeadFigure 4.1 Head structure S p i n d l eA c t u a t o r4.2.4 Actuator 4.2.3 Spindle4.2.5 Air filter 4.3 Circuit Configuration Page 4.4 Power-on Sequence Figure 4.3 Power-on operation sequence 4.5 Self-calibration 4.5.1 Self-calibration contents4.5.3 Command processing during self-calibration 4.6.1 Read/write preamplifier PreAMP 4.6 Read/write Circuit4.6.2 Write circuit 4.6.3 Read circuit Table 4.1 Transfer rate of each zone 4.6.4 Synthesizer circuit4.7 Servo Control 4.7.1 Servo control circuit Figure 4.4 Block diagram of servo control circuitServo burst capture Servoframe 96 servoframes per revolution Figure 4.5 Physical sector servo configuration on disk surface4 D/A converter DAC 5 Power amplifier2 Servo burst capture circuit 3 A/D converter ADC4.7.3 Servo frame format 4.7.2 Data-surface servo formatFigure 4.6 96 servo frames in each track 4.7.4 Actuator motor control 4.7.5 Spindle motor control 3 Stable rotation mode 2 Acceleration modeC141-E112-01EN 5.4 Command Protocol 5.5 Ultra DMA feature set 5.6 Timing CHAPTERINTERFACE 5.1 Physical Interface 5.2 Logical Interface 5.3 Host CommandsC141-E112-01EN 5.1 Physical Interface 5.1.1 Interface signalsTable 5.1 shows the interface signals Table 5.1 Interface signalsTable 5.2 Signal assignment on the interface connector 5.1.2 Signal assignment on the connectorsignal device is ready to receive Ultra DMA data out bursts. The device may register access Read or Write when the device is not ready to respond5.2.1 I/O registers 5.2 Logical InterfaceTable 5.3 I/O registers 5.2.2 Command block registers X80 Device 1 slave device Failed Diagnostic code X01 No Error Detected X02 HDC Register Compare ErrorX03 Data Buffer Compare Error X05 ROM Sum Check Error 3 Features register X1F1Bit 2 HS2 CHS mode head address 3 22. LBA bit The contents of this register indicate the device and the head numberL. 0 for CHS mode and 1 for LBA mode Bit 3 HS3 CHS mode head address 3 23. LBA bitDRDY 9 Status register X1F7C141-E112-01EN C141-E112-01EN 10 Command register X1F7Always Always5.2.3 Control block registers 5.3 Host CommandsTable 5.4 Command code and parameters 1 of 5.3.1 Command code and parametersTable 5.4 Command code and parameters 2 of Transfer sector count 5.3.2 Command descriptions1F6 HDH At command issuance I/O registers setting contents1 READ SECTORS X20 or 1F7 HCMStatus information At command completion I/O registers contents to be readError information 1F7 HSTFigure 5.1 Execution example of READ MULTIPLE command 2 Ultra DMA transfer mode ∙ The data transfer starts at the timing of DMARQ signal assertionIn LBA mode 1 Multiword DMA transfer mode1F7 HST At command completion I/O registers contents to be readError information At command issuance I/O registers setting contents1F7 HST At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsStatus information At command completion I/O registers contents to be readError information 1F7 HST∙ The data transfer starts at the timing of DMARQ signal assertion At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationR = 0 or At command completion I/O registers contents to be read 1 Multiword DMA transfer mode2 Ultra DMA transfer mode At command issuance I/O registers setting contentsAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information This command can be issued in the LBA mode10 SEEK X7x, x X0 to XF At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationError Information In LBA modeAt command issuance I/O registers setting contents At command completion I/O registers contents to be readNumber of sectors per track Table 5.5 Information to be read by IDENTIFY DEVICE command 1 ofX‘045A’ Number of cylindersX‘00’ Table 5.5 Information to be read by IDENTIFY DEVICE command 2 ofTransfer sector count currently set by READ/WRITE MULTIPLE without Table 5.5 Information to be read by IDENTIFY DEVICE command 3 ofX‘3FFF’ X‘01CA1E70’C141-E112-01EN Information to be read by IDENTIFY DEVICE command 4 of= SET MAX security extension enabled by SET MAX SET PASSWORD Table 5.5 Information to be read by IDENTIFY DEVICE command 5 ofC141-E112-01EN Table 5.5 Information to be read by IDENTIFY DEVICE command 6 of14 SET FEATURES XEF At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationX‘AA’ Table 5.6 Features register values and settable modesError information At command issuance I/O registers setting contentsxx or transfer mode At command completion I/O registers contents to be readSector Count value 15 SET MULTIPLE MODE XC6Automatic management levels Level16 EXECUTE DEVICE DIAGNOSTIC At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationTable 5.7 Diagnostic code Error information The READ LONG command supports only single sector operationAt command issuance I/O registers setting contents R = 0 or At command completion I/O registers contents to be readAt command issuance I/O registers setting contents At command issuance I/O registers setting contentsR = 0 or At command completion I/O registers contents to be read Error informationAt command completion I/O registers contents to be read At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsPeriod of timer Point of timerDisable of timer At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsError information At command issuance I/O registers setting contentsPeriod of timer At command completion I/O registers contents to be readThis command is the only way to make the device enter the sleep mode At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationThe host checks the power mode of the device with this command At command completion I/O registers contents to be readError information 27 CHECK POWER MODE X98 or XE51F7 HCM At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationTable 5.8 Features Register values subcommands and functions Error information At command issuance I-O registers setting contentsSubcommand At command completion I-O registers setting contentsTable 5.9 Format of device attribute value data Table 5.10 Format of insurance failure threshold value data Number of power-on-power-off times Read error rateSeek error rate Power-on time∙ Insurance failure threshold ∙ Raw attribute value Raw attributes data is retained∙ Failure prediction capability flag Bits 2 to 15 Reserved bits ∙ Check sumError information NOTE This command may take longer than 30 s to completeAt command issuance I/O registers setting contents At command completion I/O registers contents to be readTable 5.11 Contents of security password 1F7 HCM At command issuance I-O registers setting contentsAt command completion I-O registers setting contents Error information1F7 HCM At command issuance I-O registers setting contentsAt command completion I-O registers setting contents Error information∙ SECURITY SET PASSWORD ∙ SECURITY UNLOCK ∙ SECURITY DISABLE PASSWORD At command issuance I-O registers setting contentsAt command completion I-O registers setting contents Error informationAt command completion I-O registers setting contents SECURITY DISABLE PASSWORDSECURITY SET PASSWORD ∙ WRITE DMA At command issuance I-O registers setting contentsoperation of the lock function Table 5.12 Contents of SECURITY SET PASSWORD dataRelationship between combination of Identifier and Security level, and35 SECURITY UNLOCK F2h This command cancels LOCKED MODE At command issuance I-O registers setting contentsAt command completion I-O registers setting contents Error information1F7 HCM At command issuance I-O registers setting contentsAt command completion I-O registers setting contents Error information36-2 SET MAX SET PASSWORD F9 At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationContent At command completion I/O registers contents to be readError information SET MAX SET PASSWORD data content36-4 SET MAX UNLOCK F9 At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationError information ∙ SET MAX ADDRESS ∙ SET MAX SET PASSWORD ∙ SET MAX LOCK∙ SET MAX UNLOCK At command issuance I/O registers setting contents At command completion I/O registers contents to be readStatus information At command completion I/O registers contents to be readError information 1F7HSTTable 5.14 Command code and parameters 5.3.3 Error postingICRC 5.4.1 Data transferring commands from device to host 5.4 Command ProtocolFigure 5.2 Read Sectors command protocol 5.4.2 Data transferring commands from host to device Figure 5.3 Protocol for command abortStatus read Figure 5.4 WRITE SECTORS command protocolExpanded Figure 5.5 Protocol for the command execution without data transfer 5.4.3 Commands without data transfer5.4.5 DMA data transfer commands 5.4.4 Other commandsFigure 5.6 Normal DMA data transfer 5.5 Ultra DMA feature set 5.5.1 Overview 5.5.3 Ultra DMA data in commands 5.5.2 Phases of operation5.5.3.1 Initiating an Ultra DMA data in burst 5.5.3.2 The data in transfer 5.5.3.3 Pausing an Ultra DMA data in burst5.5.3.4 Terminating an Ultra DMA data in burst C141-E112-01EN b Host terminating an Ultra DMA data in burst5.5.4.1 Initiating an Ultra DMA data out burst 5.5.4 Ultra DMA data out commands5.5.4.2 The data out transfer 5.5.4.3 Pausing an Ultra DMA data out burst5.5.4.4 Terminating an Ultra DMA data out burst C141-E112-01EN b Device terminating an Ultra DMA data out burst5.5.5 Ultra DMA CRC rules Table 5.15 Recommended series termination for Ultra DMA 5.5.6 Series termination required for Ultra DMAFigure 5.7 Ultra DMA termination with pull-up or pull-down Figure 5.8 PIO data transfer timing 5.6 Timing 5.6.1 PIO data transfer5.6.2 Multiword data transfer Figure 5.9 Multiword DMA data transfer timing modedevice 5.6.3 Ultra DMA data transfer5.6.3.1 Initiating an Ultra DMA data in burst DMARQTable 5.16 Ultra DMA data burst timing requirements 1 of 5.6.3.2 Ultra DMA data burst timing requirementsTable 5.16 Ultra DMA data burst timing requirements 2 of tDVSIC Table 5.17 Ultra DMA sender and recipient timing requirementstDSIC tDHICDD150 at host 5.6.3.3 Sustained Ultra DMA data in burstDSTROBE at device DD150 at device DSTROBE at hostFigure 5.12 Host pausing an Ultra DMA data in burst 5.6.3.4 Host pausing an Ultra DMA data in bursttRFS DA0, DA1, DA2 CS0-, CS1 5.6.3.5 Device terminating an Ultra DMA data in burstDMARQ device DMACK- host STOP host HDMARDY- host DSTROBE device DD150STOP 5.6.3.6 Host terminating an Ultra DMA data in burstDMACK hostFigure 5.15 Initiating an Ultra DMA data out burst 5.6.3.7 Initiating an Ultra DMA data out burstDD150 host Figure 5.16 Sustained Ultra DMA data out burst 5.6.3.8 Sustained Ultra DMA data out burstHSTROBE at host DD150 at host HSTROBE at device DD150 at deviceFigure 5.17 Device pausing an Ultra DMA data out burst 5.6.3.9 Device pausing an Ultra DMA data out burstFigure 5.18 Host terminating an Ultra DMA data out burst 5.6.3.10 Host terminating an Ultra DMA data out bursttIORDYZ Figure 5.19 Device terminating an Ultra DMA data out burst 5.6.3.11 Device terminating an Ultra DMA data in burstFigure 5.20 Power-on Reset Timing 5.6.4 Power-on and reset6.6 Write Cache 6.1 Device Response to the Reset OPERATIONS6.1 Device Response to the Reset 6.2 Address Translation 6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead CacheFigure 6.1 Response to power-on 6.1.1 Response to power-onFigure 6.2 Response to hardware reset 6.1.2 Response to hardware resetFigure 6.3 Response to software reset 6.1.3 Response to software resetFigure 6.4 Response to diagnostic command 6.1.4 Response to diagnostic commandDefault parameters 6.2.1 Default parameters6.2 Address Translation 6.2.2 Logical address Figure 6.5 Address translation example in CHS mode6.3.1 Power save mode Figure 6.6 Address translation example in LBA mode 6.3 Power SaveReset hardware or software IDLE command IDLE IMMEDIATE command 1 Active modeA device enters the active mode under the following conditions ∙ A command with Seek or Write or Read is issued 2 Idle mode6.4 Defect Management 6.3.2 Power commandsDefective 6.4.1 Spare area6.4.2 Alternating defective sectors Figure 6.7 Sector slip processingFigure 6.8 Alternate cylinder assignment Figure 6.9 Data buffer configuration 6.5.1 Data buffer configuration6.5 Read-Ahead Cache 6.5.2 Caching operation 6.5.3 Usage of read segment Requested data Hit data b. Sequential hitHAP Completion of transferring requested data Read-ahead dataHAP set to hit position for data transfer Last position at previous read commandDAP Last position at previous read command 3 Full hit hit allHAP stopped Partially hit dataLack data Requested data to be transferred6.6 Write Cache When the write cache function is enabled, the transferred data from the host by the WRITE SECTORS is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function XQJ+DQV9lJ66ROOHQWXUD61 RXQJXQJ3R*X6HRXO5HSXEOLFRI.25$RQJZDON5RDG6WRFNOH\3DUN8EULGJH UDQNIXUWHU5LQJ0QFKHQ*50$15HDGHU&RPPHQWRUP 8-,768/,0,7