SED1520 Series

PIN DESCRIPTION

(1) Power Pins

Name

Description

 

 

VDD

Connected to the +5Vdc power. Common to the VCC MPU power pin.

 

 

VSS

0 Vdc pin connected to the system ground.

 

 

V1, V2, V3, V4, V5

Multi-level power supplies for LCD driving. The voltage determined for each liquid

 

crystal cell is divided by resistance or it is converted in impedance by the op amp,

 

and supplied. These voltages must satisfy the following:

 

VDD V1 V2 V3 V4 V5

 

 

(2) System Bus Connection Pins

D7 to D0

Three-state I/O.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The 8-bit bidirectional data buses to be connected to the 8- or 16-bit standard MPU

 

 

 

 

 

 

 

data buses.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

Input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Usually connected to the low-order bit of the MPU address bus and used to identify

 

 

 

 

 

 

 

the data or a command.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0=0: D0 to D7 are display control data.

 

 

 

 

 

 

 

A0=1: D0 to D7 are display data.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input.

 

 

 

 

 

 

 

 

 

 

RES

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When the

RES

signal goes

 

 

 

the 68-series MPU is initialized, and when it

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

goes

 

 

 

 

 

, the 80-series MPU is initialized. The system is reset during edge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

sense of the RES signal. The interface type to the 68-series or 80-series MPU is

 

 

 

 

 

 

 

selected by the level input as follows:

 

 

 

 

 

 

 

High level: 68-series MPU interface

 

 

 

 

 

 

 

Low level: 80-series MPU interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input. Active low. Effective for an external clock operation model only.

 

 

CS

 

 

 

 

 

 

 

An address bus signal is usually decoded by use of chip select signal, and it is

 

 

 

 

 

 

 

entered. If the system has a built-in oscillator, this is used as an input pin to the

 

 

 

 

 

 

 

oscillator amp and an Rf oscillator resistor is connected to it. In such case, the

RD,

 

 

 

 

 

 

 

 

WR and E signals must be ORed with the

CS

signals and entered.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

 

If the 68-series MPU is connected:

(RD)

 

 

 

 

 

 

 

Input. Active high.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Used as an enable clock input of the 68-series MPU.

If the 80-series MPU is connected: Input. Active low.

The RD signal of the 80-series MPU is entered in this pin. When this signal is kept low, the SED1520 data bus is in the output status.

R/W (WR)

If the 68-series MPU is connected:

 

Input.

 

Used as an input pin of read control signals (if R/W is high) or write control

 

signals (if low).

 

If the 80-series MPU is connected:

 

Input. Active low.

 

The WR signal of the 80-series MPU is entered in this pin. A signal on the data

 

bus is fetched at the rising edge of WR signal.

2–6

EPSON