SED1520 Series
PIN DESCRIPTION
(1) Power Pins
Name | Description |
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VDD | Connected to the +5Vdc power. Common to the VCC MPU power pin. |
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VSS | 0 Vdc pin connected to the system ground. |
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V1, V2, V3, V4, V5 | |
| crystal cell is divided by resistance or it is converted in impedance by the op amp, |
| and supplied. These voltages must satisfy the following: |
| VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 |
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(2) System Bus Connection Pins
D7 to D0 |
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| The | |||||||||||||||
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| data buses. |
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| A0 | Input. |
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| Usually connected to the | |||||||||||||||
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| the data or a command. |
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| A0=0: D0 to D7 are display control data. | |||||||||||||||
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| A0=1: D0 to D7 are display data. | |||||||||||||||
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RES |
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| When the | RES | signal goes |
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| goes |
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| sense of the RES signal. The interface type to the | |||||||||||||||
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| selected by the level input as follows: | |||||||||||||||
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| High level: | |||||||||||||||
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| Low level: | |||||||||||||||
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| Input. Active low. Effective for an external clock operation model only. | ||||||||||||||||
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| CS | ||||||||||||||||||||
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| An address bus signal is usually decoded by use of chip select signal, and it is | |||||||||||||||
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| entered. If the system has a | |||||||||||||||
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| oscillator amp and an Rf oscillator resistor is connected to it. In such case, the | RD, |
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| WR and E signals must be ORed with the | CS | signals and entered. | |||||||||||||
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E |
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(RD) | ||||||||||||||||||||||
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| Input. Active high. |
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| Used as an enable clock input of the |
•If the
The RD signal of the
R/W (WR) | • If the |
| Input. |
| Used as an input pin of read control signals (if R/W is high) or write control |
| signals (if low). |
| • If the |
| Input. Active low. |
| The WR signal of the |
| bus is fetched at the rising edge of WR signal. |
EPSON |