Fairchild AN-7502 manual Using the Characterization Curve, Figure, Application Note

Application Note 7502

Experimental Verification

Since the switching equations for step currents and voltages differ only by gate-current magnitudes for the same device type, one would expect a plot of switching time versus 1/RO to be of the same form as those obtained for a step current drive. This is exactly the case, as Figure 10 is merely a vari- ation of Figure 8. Using the relationships of Table 1, the observed differences between Figures 7 and 9 can be pin- pointed. The two sets of experimental curves confirm that, on the basis of the short-circuit drive current VG/RO equal- ling the constant IG, tD(on), tR, tD(off), and tF will all be longer, as predicted by the ratios of the gate drive currents of Table 1. Notice also that tR, tF switching symmetry is dis- rupted by the use of a step voltage with source resistance RO. For states 2 and 6 the time ratio is:

tTURN-ON = VG(SAT)

tTURN-OFFVG - VGS(TH)

For states 3 and 5 the time ratio is:

tTURN-ON		V
	=	G(SAT)
tTURN-OFF		VG - V

Utilization of available maximum gate drive voltage and cur- rent can be optimized for fastest power MOSFET switching speed through the use of constant-current gate drive at the expense of increased gate-drive circuit complexity.

	10
			RFM15N15
			VDD = 75V
			ID	= 7.5A
			VG	= 10V
- MICROSECONDS	1
	0.1
(t)
		DATA THEORY
		tD(OFF)
		tR
		tF
		tD(ON)
	0.01
	10-4	10-3	10-2	10-1
		1/RO

FIGURE 10. CONSTANT GATE VOLTAGE SWITCHING TIME

Using the Characterization Curve, Figure 9

To estimate the switching times for an RFM15N15 power MOSFET under the conditions VG = 10V, VDD = 75V, RO =

100 ohms, and RL = 10 ohms, precedes as follows:

State 1: MOS Off, JFET Off

This time can be estimated without recourse to the curves

t = 100(1200 x 10-12) ln [1/(1 - 4/10)]

t = 61 ns

State 2 & 6: MOS Active, JFET Active

IG = (10 - 4)/100 = 60mA
t =	(curve divisions) x IT ∝s	=	9	= 150ns
60			60

State 3: MOS Active, JFET Saturated

IG = (10 - 7)/100 = 30mA
t =	(curve divisions) x IT ∝s	=	14	= 467ns
30			30

State 4: MOS Saturated, JFET Saturated

CGS + Cx = (gate voltage slope)(test current)

=(1.5 x 10-6s/5 volts)(10mA)

=3000pF

t = 100(3000 x 10-12) ln [10/6.6] t = 125ns

State 5: MOS Active, JFET Saturated

IG = 6.6/100 = 66mA
t =	(curve divisions) x IT ∝s	=	8	= 121ns
66			66

Figure 11 shows RFM15N15 waveforms using the conditions specified in the example.

75
	VD
- VOLTS	VGS
VOLTAGE	RFM15N15
	VDD = 75 VOLTS
DRAIN	RL = 10 OHMS
	VG = 10 VOLTS
	RO = 100 OHMS
0
0	1.5	3
	TIME - MICROSECONDS

FIGURE 11. STEP GATE VOLTAGE INPUT TO AN RFM15N15

	CALCULATED	MEASURED
STATE	TIME	TIME	RATIO
	(tC, ns)	(tM, ns)	(tC/tM)
1	61	60	1.02
2 + 3	617	670	0.92
4	125	137	0.91
5 + 6	271	375	0.72

©2002 Fairchild Semiconductor Corporation Application Note 7502 Rev. A1