MB15F74UV
4. Serial Data Data Input Timing
Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of the LE signal. The following diagram shows the data input timing.
1st data |
| 2nd data | |
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Control bit | Invalid data |
Data
Clock
LE
t1
t7
MSB
t2
LSB
t3
t6
t4t5
Parameter | Min | Typ | Max | Unit |
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t1 | 20 | | | ns |
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t2 | 20 | | | ns |
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t3 | 30 | | | ns |
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t4 | 30 | | | ns |
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Parameter | Min | Typ | Max | Unit |
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t5 | 100 | | | ns |
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t6 | 20 | | | ns |
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t7 | 100 | | | ns |
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Note : LE should be “L” when the data is transferred into the shift register.
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