MB15F74UV
13
■
■■
■PHASE COMPARATOR OUTPUT WAVEFORM• LD Output Logic
Notes : • Phase error detection range = −2π to +2π
• Pulses on DoIF/RF signals during locking state are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCIN input frequency as follows.
t
WU ≥ 2/fosc : e.g. tWU ≥ 156.3 ns when fosc = 12.8 MHz
t
WU ≤ 4/fosc : e.g. tWL ≤ 312.5 ns when fosc = 12.8 MHz
IF-PLL section RF-PLL section LD output
Locking state/Power saving state Locking state/Power saving state H
Locking state/Power saving state Unlocking state L
Unlocking state Locking state/Power saving state L
Unlocking state Unlocking state L
frIF/RF
fpIF/RF
LD
DoIF/RF
tWU tWL
DoIF/RF
H
L
L
H
Z
Z
(FC bit = “1”)
(FC bit = “0”)