Fujitsu MB15F74UV manual Block Diagram

MB15F74UV

■ BLOCK DIAGRAM

VCCIF

GNDIF

(5)

(4)

PSIF (7)

Intermittent

3 bit latch

7 bit latch

11 bit latch

mode control

(IF-PLL)

LDS

SWIF

FCIF

Binary 7-bit

Binary 11-bit

Phase

Fast

Charge

Current

(6) DoIF

swallow counter

programmable

comp.

lock

pump

Switch

(IF-PLL)

counter (IF-PLL)

(IF-PLL) Tuning

(IF-PLL)

fpIF

finIF (2)

Prescaler

Lock Det.

(IF-PLL)

(IF-PLL)

XfinIF (3)

(32/33, 64/65)

2 bit latch

14 bit latch

1 bit latch

LDIF

Binary 14-bit pro-

C/P setting

T1

T2

grammable ref.

counter

counter(IF-PLL)

frIF

OSCIN (18)

Fast

lock

Tuning

frRF

AND

Selector

LD

Binary 14-bit pro-

T1

T2

C/P setting

frIF

grammable ref.

(8) LD/

OR

counter

frRF

counter (RF-PLL))

fpIF

fout

2 bit latch

14 bit latch

1 bit latch

fpRF

LDRF

finRF (14)

Prescaler

fpRF

Lock Det.

(RF-PLL)

XfinRF (13)

(RF-PLL)

(64/65, 128/129)

LDS

SWRF

FCRF

Binary 7-bit

Binary 11-bit

Phase

Fast lock Tuning

Charge

Current

(10) DoRF

Intermittent

comp.

swallow counter

programmable

pump

Switch

PSRF (9)

mode control

(RF-PLL)

counter (RF-PLL)

(RF-PLL)

(RF-PLL)

(RF-PLL)

3 bit latch

7 bit latch

fpRF

11 bit latch

LE (15)

Schmitt

trigger

Latch selector

circuit

Schmitt

Data (16)

trigger

C

C

circuit

N

N

23-bit shift register

Schmitt

Clock(17)

1

2

trigger

circuit

(1)

(11)

(12)

GND

VCCRF

GNDRF

4