Table 2: Main components of the Intel Itanium Server Blade

Component

Manufacturer

Quantity

Description

 

 

 

 

Bridge

Intel

1

PCIe to PCI-X bridge

 

 

 

 

South Bridge

Intel

1

South bridge — connects legacy devices

 

 

 

 

SIO

SMSC

1

Super I/O chip — contains the COM port

 

 

 

and other legacy devices

 

 

 

 

FW ROM

ATMEL/

8 MB

A flash ROM storing the images of system

 

STMicro

 

firmware

 

 

 

Also used as NVRAM under the control of

 

 

 

the system firmware

 

 

 

 

Gigabit

Intel

1

Gigabit Ethernet interface controller, two

Ethernet

 

 

ports, SerDes connection

 

 

 

Wake on LAN supported

 

 

 

TagVLAN supported

 

 

 

PXE Boot supported

 

 

 

 

USB controller

VIA

1

Compatible to UHCI and EHCI

 

 

 

 

BMC

Renesas

1

Management processor

 

 

 

 

BMC SRAM

Renesas

2 MB, with

Main memory for management processor

 

 

parity

 

 

 

 

 

FPGA

Xilinx

1

Controls the BMC bus, decodes addresses

 

 

 

and functions as a bridge for LPC

 

 

 

 

Flash ROM

Fujitsu

16 MB

Backs up BMC codes and SAL

 

 

 

 

BUS SW

 

1

Reserved for the SVP duplex (future)

switching over

 

 

 

BMC-SVP

 

 

 

 

 

 

 

Intel Itanium Processor 9100 Series

The Dual-Core Intel Itanium 9100 series 64-bit processor delivers scalable performance with two high- performance cores per processor, memory addressability up to 1024 TB, 24 MB of on-die cache, and a 667 MHz front-side bus. It also includes multi-threading capability (two threads per core) and support for virtualization in the silicon.

Explicitly Parallel Instruction Computing (EPIC) technology is designed to enable parallel throughput on a enormous scale, with up to six instructions per clock cycle, large execution resources

(128 general-purpose registers, 128 floating point registers and 8 branch registers) and advanced capabilities for optimizing parallel throughput.

The processors deliver mainframe-class reliability, availability, and serviceability features with advanced error detection and correction and containment across all major data pathways and the cache subsystem. They also feature integrated, standards-based error handling across hardware, firmware, and the operating system.

10 BladeSymphony 1000 Architecture White Paper

www.hitachi.com

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Hitachi 1000 manual Intel Itanium Processor 9100 Series, FW ROM Atmel