40. POST Codes
Please take reference to
http://www.phoenix.com/en/Customer+Services/BIOS/AwardBIOS/Award+Error+Codes.ht m
40.1Normal POST Code
Note: EISA POST codes are typically output to port address 300h. ISA POST codes are output to
port address 80h.
Code (hex) | Name | Description |
C0 | Turn Off Chipset and | OEM |
| CPU test | Processor Status (1FLAGS) Verification. Tests the following |
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| processor status flags: Carry, zero, sign, overflow, the BIOS sets |
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| each flag, verifies They are set, then turns each flag off and |
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| verifies it is off. |
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| Read/Write/Verify all CPU registers except SS, SP, and BP with |
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| data pattern FF and 00. RAM must be periodically refreshed to |
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| keep the memory from decaying. This function ensures that the |
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| memory refresh function is working properly. |
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C1 | Memory Presence | First block memory detect OEM |
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| memory. Early chip set initialization Memory presence test OEM |
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| chip set routines clear low 64K of memory Test first 64K memory. |
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C2 | Early Memory | OEM Specific- Board Initialization |
| Initialization |
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C3 | Extend Memory DRAM | OEM Specific- Turn on extended memory Initialization |
| select | Cyrix CPU initialization, Cache initialization |
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C4 | Special Display | OEM Specific- Display/Video Switch handling so that switch |
| Handling | handling display switch errors never occurs |
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C5 | Early Shadow | OEM specific- Early shadow enable for fast boot |
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C6 | Cache presence test | External cache size detection |
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CF | CMOS Check | CMOS checkup |
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B0 | Spurious | If interrupt occurs in protected mode. |
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B1 | Unclaimed NMI | If unmasked NMI occurs, display Press F1 to disable NMI, F2 |
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| reboot. |
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BF | Program Chip Set | To program chipset from defaults values |
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Setup Pages | E1- Page 1, E2 - Page 2, etc. | |
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1 | Force load Default to | Chipset defaults program |
| chipset |
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2 | Reserved |
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102