ECM-5510 2.4.19.1.3Commands

 

Signal

 

Signal Description

 

 

 

This is an active high signal used to latch valid addresses from the current bus

 

BALE

 

master on the falling edge of BALE. During DMA, refresh and alternate master

 

 

cycles, BALE is forced high for the duration of the transfer. BALE is driven by the

 

 

 

 

 

 

permanent master with a totem-pole driver.

 

 

 

This is an active low signal driven by the current master to indicate an I/O read

 

 

 

operation. I/O mapped devices using this strobe for selection should decode

 

IOR#

 

addresses SA [15:0] and AEN. Additionally, DMA devices will use IOR# in

 

 

 

conjunction with DACKn# to decode a DMA transfer from the I/O device. The

 

 

 

current bus master will drive this line with a tri-state driver.

 

 

 

 

 

 

 

This is an active low signal driven by the current master to indicate an I/O write

 

 

 

operation. I/O mapped devices using this strobe for selection should decode

 

IOW#

 

addresses SA [15:0] and AEN. Additionally, DMA devices will use IOR# in

 

 

 

conjunction with DACKn# to decode a DMA transfer from the I/O device. The

 

 

 

current bus master will drive this line with a tri-state driver.

 

 

 

This is an active low signal driven by the permanent master to indicate a memory

 

 

 

read operation in the first 1MB of system memory. Memory mapped devices using

 

SMEMR#

 

this strobe should decode addresses SA [19:0] only. If an alternate master drives

 

 

MEMR#, the permanent master will drive SMEMR# delayed by internal logic. The

 

 

 

 

 

 

permanent master ties this line to VCC through a pull-up resistor to ensure that it is

 

 

 

inactive during the exchange of bus masters.

 

 

 

 

 

 

 

This is an active low signal driven by the permanent master to indicate a memory

 

 

 

write operation in the first 1MB of system memory. Memory mapped devices using

 

SMEMW#

 

this strobe should decode addresses SA [19:0] only. If an alternate master drives

 

 

MEMR#, the permanent master will drive SMEMR# delayed by internal logic. The

 

 

 

 

 

 

permanent master ties this line to VCC through a pull-up resistor to ensure that it is

 

 

 

inactive during the exchange of bus masters.

 

 

 

This is an active low signal driven by the current master to indicate a memory read

 

 

 

operation. Memory mapped devices using this strobe should decode addresses

 

MEMR#

 

LA [23:17] and SA [19:0]. All bus masters will drive this line with a tri-state driver.

 

 

 

The permanent master ties this line to VCC through a pull-up resistor to ensure

 

 

 

that it is inactive during the exchange of bus masters.

 

 

 

 

 

 

 

This is an active low signal driven by the current master to indicate a memory write

 

 

 

operation. Memory mapped devices using this strobe should decode addresses

 

MEMW#

 

LA [23:17] and SA [19:0]. All bus masters will drive this line with a tri-state driver.

 

 

 

The permanent master ties this line to VCC through a pull-up resistor to ensure

 

 

 

that it is inactive during the exchange of bus masters.

 

 

 

 

46 ECM-5510 User’s Manual