
User’s Manual
2.4.19.1Signal Description – PC/104 Connector (CN7 + CN8) 2.4.19.1.1Address
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| Signal Description |
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| The address signals LA [23:17] define the selection of a 128KB section of memory |
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| space within the 16MB address range of the |
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| active high. The validity of the MEMCS16# depends on these signals only. These |
| LA [17:23] |
| address lines are presented to the system with |
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| master drives these lines except when an alternate master cycle occurs; in this |
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| case, the temporary master drives these lines. The LA signals are not defined for |
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| I/O accesses. |
| SA [0:19] |
| System address. Address lines for the first one Megabyte of memory. SA [9:0] |
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| used for I/O addresses. SA0 is the least significant bit | |
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| This signal is an active low signal, that indicates that a byte is being transferred on |
| SBHE# |
| the upper byte (SD [15:8]) of the 16 bit bus. All bus masters will drive this line with |
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2.4.19.1.2Data
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| Signal Description |
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| These signals are defined for the low order byte of the | ||||||||||||||||
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| only bus for 8 bit | ||||||||||||||||
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| part of the data bus are defined for | ||||||||||||||||
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| and for | ||||||||||||||||
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| used to define the data present on this bus: |
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| SBHE# |
| SA0 |
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| Action |
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| SD [0:7] |
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| EVEN |
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| Word transfer |
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| Byte transfer on |
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| Byte transfer on |
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| Byte transfer on |
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| SD7- |
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| SD [8:15] |
| These signals are defined for the high order byte of the | ||||||||||||||||
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| I/O transfers on this part of the bus are defined when SBHE# is active. | |||||||||||||||||
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