GMS90X5XC Series HYUNDAI MicroElectronics
Jan. 2001 Ver 1.0 41

Figure 9. AC Testing: Input, Output Waveforms

Figure 10. Float Waveforms

Figure 11. External Clock Cycle

AC Inputs during testing are driven at VCC−0.5V for a logic ‘1’ and 0.45V for a logic ‘0’.

0.2VCC + 0.9
0.2VCC − 0.1
Test Points
VCC−0.5V
0.45V

Timing measurements are made a VIHmin for a logic ‘1’ and VILmax for a logic ‘0’.

VLOAD + 0.1
VLOAD − 0.1
Timing Reference Points
0.2VCC − 0.1
VOH − 0.1
VOL + 0.1
VLOAD

For timing purposes a port pin is no longer floating when a 100mV change from load voltage

IOL / IOH ≥ 20mA.

occurs and begins to float when a 100mV change from the loaded VOH / VOL level occurs.

tCHCL tCLCH
tCHCX
tCLCL
tCLCX
0.2 VCC −0.1
0.7 VCC
VCC−0.5V
0.45V