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3.Sends the EOI
4.Waits one I/O delay
5.Enables the interrupt through the Set Interrupt Enable Flag command
Hardware interrupt IRQ9 is defined as the replacement interrupt level for the cascade level IRQ2. Program interrupt sharing is implemented on IRQ2, interrupt hex 0A. The following processing occurs to maintain compatibility with the IRQ2 used by IBM Personal Computer products:
1.A device drives the interrupt request active on IRQ2 of the channel.
2.This interrupt request is mapped in hardware to IRQ9 input on the second interrupt controller.
3.When the interrupt occurs, the system microprocessor passes control to the IRQ9 (interrupt hex 71) interrupt handler.
4.This interrupt handler performs an EOI command to the second interrupt controller and passes control to the IRQ2 (interrupt hex 0A) interrupt handler.
5.This IRQ2 interrupt handler, when handling the interrupt, causes the device to reset the interrupt request before performing an EOI command to the master interrupt controller that finishes servicing the IRQ2 request.
Software compatibility
To maintain software compatibility, the interrupt polling mechanism that is used by IBM Personal Computer products is retained. Software that interfaces with the reset port for the IBM Personal Computer
Software interrupts
With the advent of software interrupt sharing, software interrupt routines must daisy chain interrupts. Each routine must check the function value, and if the function value is not in the range of function calls, that routine must transfer control to the next routine in the chain. Because software interrupts are initially pointed to address 0:0 before daisy chaining, check for this case. If the next routine is pointed to address 0:0 and the function call is out of range, the appropriate action is to set the carry flag and initiate a RET 2 to indicate an error condition.
Machine-sensitive programs
Programs can select
32PC 300 GL and 300 PL