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Intel 21555 manual Interrupt Routing, Introduction, Interrupt ORing

Models: 21555

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Introduction

1.8Interrupt Routing

Table 6 shows the ORing of interrupts. 12 interrupts are connected to each of three secondary bus PCI slots but four (4) interrupts are driven to the card edge. The 12 incoming interrupts must be combined. Interrupt ORing is in accordance with the PCI-to-PCI Bridge Architecture Specification revision 1.1.

Table 6. Interrupt ORing

Device Number	Interrupt Pin on	Interrupt Pin on Board
Device Number	Device	Connector
	Device	Connector

	INTA#	INTB#
5	INTB#	INTC#
(Optional slot J101)	INTC#	INTD#
	INTD#	INTA#

	INTA#	INTA#
6	INTB#	INTB#
(PICMG slot J101)	INTC#	INTC#
	INTD#	INTD#

	INTA#	INTD#
7	INTB#	INTA#
(Top slot J7)	INTC#	INTB#
	INTD#	INTC#

21555 PCI-to-PCI Bridge Evaluation Board User’s Guide

Page 13

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Intel 21555 manual Interrupt Routing, Introduction, Interrupt ORing

Contents

21555 PCI-to-PCI Bridge Evaluation Board User’s GuideNovember 21555 PCI-to-PCI Bridge Evaluation Board User’s Guide Figures ContentsJ21 Switch Operations for Central Function and Arbiter Control TablesSwitch Operations for Synchronous or Asynchronous Clock Control Introduction 1.2 Features1.1 Overview 1.3 Major Components 1.3.1 ConnectorsIntroduction 1.3.3 Devices 1.3.2 Switches and JumperIntroduction Figure 2. Switches 1.4 Switch SettingsIntroduction Table 1. DIP Switch Operation 1.5 Stake-Pin JumperIntroduction Table 2. Stake-Pin Jumper a21555 1.6 Resistor JumpersIntroduction Figure 3. Jumper Resistors1.6.2 Clamping Voltage 1.6.1 Clock ConfigurationTable 3. Clock Configuration Jumpers IntroductionIntroduction 1.7 Secondary Slot Numbering and IDSEL MappingFigure 4. Local PCI Slot Numbering Table 5. Slot and IDSEL MappingIntroduction 1.8 Interrupt RoutingTable 6. Interrupt ORing Introduction 1.9 Typical Configurations21555 PCI-to-PCI Bridge Evaluation Board User’s Guide 21555Figure 6 shows the DE1B55503 with two local bus option cards IntroductionFigure 6. DE1B55503 with Two Local Bus Option Cards 21555 PCI-to-PCI Bridge Evaluation Board User’s GuidePage 2.2 Hardware Requirements Operations and Installation2.3 Software Requirements 2.1 Specifications2.3.1 Programming the SROM Operations and Installation2.3.2 Programming the Flash ROM 2.3.2.1 Board Setup 2.4 Installation ProcedureOperations and Installation 2.3.2.2 Running DbFlash.exeOperations and Installation 2.5 Interrupt RoutingTable 9. Interrupt ORing 3.1 PICMG Configuration Optional Configurations3.2 Central Function and Arbiter Control 3.3 Asynchronous Clocking Optional ConfigurationsA.1 J2 J4, J5, and J6 Connector Pinouts Signal and Default Information21555 PCI-to-PCI Bridge Evaluation Board User’s Guide Table A-2. J4 Pin Assignments Signal and Default InformationTable A-3. J5 CBE, REQ, and GNT 21555 PCI-to-PCI Bridge Evaluation Board User’s Guide Signal and Default InformationLSTAT A.3 Factory Default Switch and Jumper Configuration A.2 JATAG Connector PinoutSignal and Default Information Table A-5. J1 JATAG Connector