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Intel 21555 manual Signal and Default Information, PCI-to-PCI Bridge Evaluation Board User’s Guide

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Signal and Default Information

Table A-3. J5 CBE, REQ, and GNT

Schematic			Mictor		Mictor	Schematic
Signal Name			Pin Number		Pin Number	Signal Name

			23		24
	S_REQ8		23		24		S_GNT1

			25		26
	S_REQ7		25		26		S_GNT0

			27		28	S_M66ENA
	S_REQ6		27		28	S_M66ENA

			29		30
	S_REQ5		29		30			S_PNE

			31		32
	S_REQ4		31		32

			33		34		S_CLKI
	S_REQ3		33		34		S_CLKI

			35		36	SCLK_O
	S_REQ2		35		36	SCLK_O

			37		38
	S_REQ1		37		38

Table A-4gives the Mictor connectors pin assignment and DE1B55503 schematic signal names.

Table A-4. J6, Parallel ROM and Control

Schematic							Mictor		Mictor			Schematic
Signal Name							Pin Number		Pin Number	Signal Name

		+5V					1		2								SCL

		GND					3		4								SDA

S_CLK0_2							5		6			S_CLK0_3
		CLK					5		6								CLKB
		CLK															CLKB

PR_AD7							7		8
PR_AD7							7		8				S_FRAME

PR_AD6							9		10
PR_AD6							9		10							S_IRDY

PR_AD5							11		12
PR_AD5							11		12			S_DEVSEL

PR_AD4							13		14
PR_AD4							13		14							S_TRDY

PR_AD3							15		16
PR_AD3							15		16							S_STOP

PR_AD2							17		18								S_PAR

PR_AD1							19		20
PR_AD1							19		20							S_SERR

PR_AD0							21		22
PR_AD0							21		22						S_PERR

DB_SAC5							23		24
DB_SAC5							23		24				S_REQ64

							25		26
		PR_CS					25		26					S_ACK64

PR_CLK							27		28
PR_CLK							27		28					S_PAR54

							29		30
	PR_ALE						29		30

							31		32
		PR_RD					31		32								S_RST

							33		34
	PR_WR						33		34		PICMG_RST

							35		36							L_STAT

							37		38					P_ENUM

21555 PCI-to-PCI Bridge Evaluation Board User’s Guide

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Intel 21555 manual Signal and Default Information, PCI-to-PCI Bridge Evaluation Board User’s Guide, Lstat

Contents

21555 PCI-to-PCI Bridge Evaluation Board User’s GuideNovember 21555 PCI-to-PCI Bridge Evaluation Board User’s Guide Figures ContentsJ21 Switch Operations for Central Function and Arbiter Control TablesSwitch Operations for Synchronous or Asynchronous Clock Control Introduction 1.2 Features1.1 Overview 1.3 Major Components 1.3.1 ConnectorsIntroduction 1.3.3 Devices 1.3.2 Switches and JumperIntroduction Figure 2. Switches 1.4 Switch SettingsIntroduction Table 1. DIP Switch Operation 1.5 Stake-Pin JumperIntroduction Table 2. Stake-Pin Jumper a21555 1.6 Resistor JumpersIntroduction Figure 3. Jumper Resistors1.6.2 Clamping Voltage 1.6.1 Clock ConfigurationTable 3. Clock Configuration Jumpers IntroductionIntroduction 1.7 Secondary Slot Numbering and IDSEL MappingFigure 4. Local PCI Slot Numbering Table 5. Slot and IDSEL MappingIntroduction 1.8 Interrupt RoutingTable 6. Interrupt ORing Introduction 1.9 Typical Configurations21555 PCI-to-PCI Bridge Evaluation Board User’s Guide 21555Figure 6 shows the DE1B55503 with two local bus option cards IntroductionFigure 6. DE1B55503 with Two Local Bus Option Cards 21555 PCI-to-PCI Bridge Evaluation Board User’s GuidePage 2.2 Hardware Requirements Operations and Installation2.3 Software Requirements 2.1 Specifications2.3.1 Programming the SROM Operations and Installation2.3.2 Programming the Flash ROM 2.3.2.1 Board Setup 2.4 Installation ProcedureOperations and Installation 2.3.2.2 Running DbFlash.exeOperations and Installation 2.5 Interrupt RoutingTable 9. Interrupt ORing 3.1 PICMG Configuration Optional Configurations3.2 Central Function and Arbiter Control 3.3 Asynchronous Clocking Optional ConfigurationsA.1 J2 J4, J5, and J6 Connector Pinouts Signal and Default Information21555 PCI-to-PCI Bridge Evaluation Board User’s Guide Table A-2. J4 Pin Assignments Signal and Default InformationTable A-3. J5 CBE, REQ, and GNT 21555 PCI-to-PCI Bridge Evaluation Board User’s Guide Signal and Default InformationLSTAT A.3 Factory Default Switch and Jumper Configuration A.2 JATAG Connector PinoutSignal and Default Information Table A-5. J1 JATAG Connector