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Intel 21555 manual Tables, J21 Switch Operations for Central Function and Arbiter Control

Models: 21555

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Tables

1	DIP Switch Operation	9
2	Stake-Pin Jumper	9
3	Clock Configuration Jumpers	11
4	Voltage Clamp	11
5	Slot and IDSEL Mapping	12
6	Interrupt ORing	13
7	Switch Operation for SROM programming	18
8	Switch Operation for FLASH programming	19
9	Interrupt ORing	20
10	J9 PICMG Switches	21
11	Clock Routing Zero Ohm Resistors	21
12	External Arbiter Switch Option	22
13	J21 Switch Operations for Central Function and Arbiter Control	22
14	Switch Operations for Synchronous or Asynchronous Clock Control	22

iv	21555 PCI-to-PCI Bridge Evaluation Board User’s Guide

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Intel 21555 manual Tables, J21 Switch Operations for Central Function and Arbiter Control

Contents

21555 PCI-to-PCI Bridge Evaluation Board User’s GuideNovember 21555 PCI-to-PCI Bridge Evaluation Board User’s Guide Contents FiguresJ21 Switch Operations for Central Function and Arbiter Control TablesSwitch Operations for Synchronous or Asynchronous Clock Control Introduction 1.2 Features1.1 Overview 1.3 Major Components 1.3.1 ConnectorsIntroduction 1.3.3 Devices 1.3.2 Switches and JumperIntroduction Figure 2. Switches 1.4 Switch SettingsIntroduction 1.5 Stake-Pin Jumper Table 1. DIP Switch OperationIntroduction Table 2. Stake-Pin Jumper a1.6 Resistor Jumpers 21555Introduction Figure 3. Jumper Resistors1.6.1 Clock Configuration 1.6.2 Clamping VoltageTable 3. Clock Configuration Jumpers Introduction1.7 Secondary Slot Numbering and IDSEL Mapping IntroductionFigure 4. Local PCI Slot Numbering Table 5. Slot and IDSEL MappingIntroduction 1.8 Interrupt RoutingTable 6. Interrupt ORing 1.9 Typical Configurations Introduction21555 PCI-to-PCI Bridge Evaluation Board User’s Guide 21555Introduction Figure 6 shows the DE1B55503 with two local bus option cardsFigure 6. DE1B55503 with Two Local Bus Option Cards 21555 PCI-to-PCI Bridge Evaluation Board User’s GuidePage Operations and Installation 2.2 Hardware Requirements2.3 Software Requirements 2.1 Specifications2.3.1 Programming the SROM Operations and Installation2.3.2 Programming the Flash ROM 2.4 Installation Procedure 2.3.2.1 Board SetupOperations and Installation 2.3.2.2 Running DbFlash.exeOperations and Installation 2.5 Interrupt RoutingTable 9. Interrupt ORing 3.1 PICMG Configuration Optional Configurations3.2 Central Function and Arbiter Control Optional Configurations 3.3 Asynchronous ClockingA.1 J2 J4, J5, and J6 Connector Pinouts Signal and Default Information21555 PCI-to-PCI Bridge Evaluation Board User’s Guide Table A-2. J4 Pin Assignments Signal and Default InformationTable A-3. J5 CBE, REQ, and GNT 21555 PCI-to-PCI Bridge Evaluation Board User’s Guide Signal and Default InformationLSTAT A.2 JATAG Connector Pinout A.3 Factory Default Switch and Jumper ConfigurationSignal and Default Information Table A-5. J1 JATAG Connector